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Deficient LMZ12001

Other Parts Discussed in Thread: LMZ12001, LM3881, LMZ12002

Hello,

I use the LMZ12001 since 2 years and since 2 months I note a problem with this component.

This component is used to generate a 1V2 and a 3V3 for a Altera FPGA and I have a problem on the 3V3.

I have the feeling that at low current the LMZ12001 is not able to work correctly (only since 2 month, before, I had no problem!).

I did these tests :

- I have 5 x 22uF ceramic capacitor on the output and when I increase this value (to 300-500uF) it seems to be good.

- My input voltage is 12V, when I decrease to 5-6V, it seems to be good.

- When I heat the board, it seems to be good. (Integrated inductor whom the values changes with the temperature ? ...)

I see the good working or not of the product because the FPGA on the board resets. I'm sure sure sure that's the LMZ12001 which is deficient (I took 2 boards, one OK and the other one KO, I swapped all components and when I swapped the LMZ12001 the problem changes of boards, the test was done 4-5 times).

It's a big big problem, I'm not sur to have a perennial solutions as part of the 3 solutions quoted above and it's not normal to change everything after 2 years of good working.

I add that I bought maybe 15-20 LMZ12001 at Radiospares and Mouser to test it and I have 40-50% of deficient products.

Is it possible to check this quickly please ?

Best Regards,

  • Please send us more details about this issue; Input and output voltage range and load range, scope shots of the output voltage, temperature range, etc.  Also, you may want to hold a scope probe above the package to sense the internal switching and take a shot of that.   It seems to me that using a 300uF to 500uF output cap is a little too big.

    F.D.

     

  • The input voltage is 12V.

    The output voltage is 3V3.

    The current range is from 150 to 250mA (on the 3V3).

    The ambient temperature range is 20-25°C (temperature of the office...)

    I'm agree with you, these values of output cap are so big for a DC/DC converter, and especially it worked with 5x22uF since 2 years.

    Here screenshots of the internal switching (scope probe above the package):

    - Abnormal converter (5x22uF / AC measurement)   (frequency of square wave = 540KHz ; frequency of sinus wave = 2.3MHz)

    - -Normal converter (5x22uF / AC measurement)   (frequency of square wave = 542KHz ; frequency of sinus wave = 2MHz)

    - Abnormal converter coorected with 5x100uF cap (5x100uF / AC measurement)   (frequency of square wave = 570KHz ; frequency of sinus wave = 2.23MHz)

    The amplitude of the signal is different because of positioning of the probe.

  • Please send your schematic and a PDF of your PCB layout.

    Can you send a plot of the output voltage when the issue is seen? Is Vout too low or too high??, etc.

    What load do you see the issue ??

    F.D.

     

  • Is it possible to send PCB layout and doc via a private mail please ?

    We don't see any difference on the regulated output voltage between 5x22uF KO, 5x22uF OK and 5x100uF OK.

    We see the problem thanks to the FPGA wich resets forever (maybe every 50ms). I saw the output voltage with a big timebase (1s/div) and no glitch or low voltage. It's because of that it was difficult to find the origin of the problem.

    Here a plot of LMZ12001 with 5x22uF KO:

    Here a plot of LMZ12001 with 5x22uF OK:

    Here a plot of LMZ12001 with 5x100uF OK:

  • You can send you data to simpleswitcherapps@ti.com

    It is hard to understand how the regulator can be resetting the uP if the output voltage is never glitching ??

    One thing is to be sure that the EP is soldered down correctly, since it provides an electrical connection to ground as well as a thermal connection.

    FD

  • Yes it was hard because electricaly all seems OK, it 's just when I change the LMZ12001 that it reworks. So I think the problem is from the current delivered by the regulator (maybe compensed by the increase of the ouput capacitor to 500uF ?)

    I'm sur the EP is soldered correctly. From the beginning it's the same EMS which wired the board with this regulator and no change during this time.

    The tests was made by this EMS which have an IR machine to soldered and desoldered the EP. We did a test with a bad LMZ12001 : we bought 8 LMZ12001 at radiospares and tested it on the board, maybe 3-4 was deficient, the others was correct.

    In more with a deficient LMZ12001, we just change the 5x22uF to 5x100uF output cap and it reworks, I don't think that this change can mask or resolve an EP soldering problem ?

  • What is the purpose of the LDO?  Is the LDO on at the same time as the DC/DC ??

    FD

  • The LDO is on at the same time but I don't know why he's here, I'm not the designer of the board. Maybe to add current when needed...So I test with removing this LDO and no effect on bad LMZ12001.

  • Do you have a POR circuit connected to Vout that could reset the uP ??

    The LDO and DC/DC will fight to control the output voltage when they are both on; so this sounds like a bad idea to us.

    It could be that any POR circuit you have may be set too low and resetting the uP when it should not.

    You might try slightly increasing the output of the DC/DC using the FB dividers as a test to see if the output is too close to the POR set point.

    FD

  • Hello,

    I don't forget to reply, I don't just have the time, I hope to reply at your requests friday!

    Thank you.

    EDIT:

    Do you have a POR circuit connected to Vout that could reset the uP ??


    There is no POR circuit but a "Power Sequencer" LM3881. I check this component and all are OK.

    The LDO and DC/DC will fight to control the output voltage when they are both on; so this sounds like a bad idea to us

    I'm agree with you with the DC/DC and LDO but the problem don't come from this. I forget: when I remove the DC/DC, the FPGA reworks correctly (the LDO substitutes for DC/DC) but it's not viable, the current is too strong and the LDO overheats. But that show that the problem is about the LMZ12001.

    You might try slightly increasing the output of the DC/DC using the FB dividers as a test to see if the output is too close to the POR set point.


    What intereset ? there is no POR circuit.

    But I can say when I increase the output current (adding a resistor in // with output) the problem disappears.

  • If the output of the DC/DC is OK, then I do not see what is resetting the uP. 

    Please try using just the DC/DC without the LDO and see if that is OK.

    FD

  • I already tested without the LDO, no improvement. However without the LMZ12001, the LDO reworks correctly.


    As I said previously, when I increase the current supplied by the LMZ12001 (with a 33R resistor in parallel on his output) it seems to rework correctly. And when I increase the output capacitor from 5x22uF to 5x100uF, the same.

  • It sounds like there are some pulse of current that might be dragging down the supply; even though you can not see them on the scope???

    If larger output capacitor helps then I would check to make sure the regulator is stable with that and it starts up OK.

    FD

     

  • I confirm, I don't see negative glitch on the regulated output (confirmed by our EMS). So on myreply of Jul 9, 2015 5:08 PM we see nothing on the scopeshoots.
  • Hello,

    I come back about this subject. Sorry for the time since the last answer, I was in vacation and another priority subjects to treat before this one.

    So , I increased the output voltage to 3V6 (with a potentiometer) which is the upper limit of the FPGA and no effect, the FPGA always resets constantly. (for the test I removed the LDO MIC5209 in parallel of the LMZ12001).

  • Hello,

    No more suggestion about this problem ?
  • Samuel,

    The LMZ12001 is used to power FPGA via an LDO. The FPGA resets frequently at some boards. When the LMZ12001 was swapped the issue was fixed. Is that correct?

    Have you compared the Vout waveforms at the moment FPGA resets to the Vout waveform on a good board? If Vout looks clean, it is hard to believe the LMZ12001 is the reason. There has to be some difference observable between the good boards and the trouble boards.

    What would make the FPGA reset? Vout dip? Ground noise?

    How much current does the FPGA need at peak speed? If the FPGA is overloading the LMZ12001, voltage droop should be observed at the output.

    -Yang

     

     

  • 1) Yes when I swapp the LMZ12001 with one of a good board, the trouble board reworks correctly (this the reason that I said the problem come from the LMZ12001). So when I want to change a bad LMZ12001 with a new LMZ12001 (bought in the business), I need to test several LMZ12001 because on 10 parts, maybe 7-8 don't work properly (same symptom).

    2)This is the difficulty, as I said on previous post, when the FPGA resets the output voltage are the same like a good board, no difference.
    I say LMZ12001 is the reason, because swapping all components between a trouble and good board, it's only when I swapp the LMZ12001 that the trouble board reworks correctly.

    3) I don't know why the FPGA rese, but I see the reset thanks to the state of several outputs. For example, the heartbeat (output of the FPGA) blinks chaotically, same with a output controlling a ON/OFF pin of another LDO. I can see the output at the scope. Last point, when I want to control the FPGA with a "signal tap", I connect my PC to him but just after I'm deconnected.

    4) There's no visible voltage drop at Vout. So I don't think the LMZ12001 is overloading because there's a 500mA capability LDO in parallel and when I remove the LMZ12001, the LDO supplies the FPGA correctly (resets of FPGA disappear). I advise that when I do the test this LDO is removed.


    I add that it's not possible to only use the LDO without LMZ12001, because the power through the LDO is too important and it heats up. In more I tested LMZ12002 and I have the same problem.

    This is strange because this problem appears suddenly in this middle year and since 2-3 years with this part no problem.

    In a previous post, I said when I add resistor in parallel of the output to increase the consumed current (50-100mA in more), the problem disappears, so yesterday I had 2 boards where this test didn't work and when the effect of the 5x100uF (instead of 5x22uF) don't work too.
  • I cannot explain why your system worked for two years and suddenly start to have trouble. Is there any other BOM change? What I can do is to review your schematic and layout to see there's any warning sign or not.

    If no instability and no over/undershoot can be observed on the output of the LMZ12001, I suspect noise on the PCB board, which could come from improper bypassing, layout, etc. Please include the details of the capacitor at the input and output of the LMZ12001 and at the input of the FPGA.

    -Yang

  • Sorry for this late reply.


    I go to see if I can transmit schematic and layout.

    About decoupling :


    - At the input of the LMZ12001, I have a 22uF/16V/X7R capacitor.

    - At the output of the LMZ12001, I have the same in five copy  22uF/16V/X7R, actually the value is 100uF/6V3/X5R to work the board.

    - At the input of the FPGA, I have a 100nF/50V/X7R capacitor for each supply pin (36 supply pins --> 36 capacitors of 100nF)

  • Since your input voltage is 12V, the 16V rated 22uF ceramic capacitor will derate significantly. Some capacitor manufacture has derating curves or calculators on their website. With aging, the caps could derate even more, resulting in inefficient decoupling at the input side of the buck regulator.

    I'd sugguest to use at least 25V rated 22uF ceramic capacitor at the input side, plus a 100nF 50V cap, as close as possible to the VIN and GND pins. Better bypassing at Vin to ground should help.

    16V capacitors at the outputs are fine.

    -Yang

  • 1- I understand, but the problem occurs on new PCB board (just wired by our EMS = 0 hours of using). But I can try to add a second 22uF in parrallel at the first to compensate the derating.

    2- OK I will try to add a 100nF cap at the input.

    I come back to you witth the results.

    Thank you,
  • Come back about the test:

    - Add a second 22uF and a 100nF at Vin don't solve the problem.

    I see if it's possible to send board layout to check by you.
  • Yes, I can check your board schematic and layout.
  • Have you an mail on which I can send the files ?

    Is it OK if the schematics and layout are in pdf ?
  • Please send them over to simpleswitcherapps@ti.com
    PDF is ok as long as we can identify the components. -Yang
  • Have you received the pdf ?
  • Yes, we are looking into it.
  • Looking at the schematic, I can see the same design is used for 1.2V and 3.3V rails. The on time will be the same and the switching frequency will be much higher with the 3.3V rail. I also noticed that the output capacitors are both 500uF. The datasheet recommandation is 100uF Cout.

    The layout is not optimized. For the Cin and Cout, it is the best to connect the ground size of the caps to the EP of the module on the top layer. That creates a return loop for the high frequency noise with minimum parasitic inductance.

    It is hard to see how the power is routed to the FPGA. Do you have any bypass caps at the VCC pin of the FPGA? Please try to add 1uF by pass cap there. I don't know why the FPGA could reset when you cannot observe any issue at the output of the LMZ.

    Yang

     

  • - I know the recommandation is 100uF but with 100uF there is the problem and I can resolve it (or mask it) with 500uF.

    - Ground of Cout are connected to EP of the module on the Top Layer, effectively for Cin it's not the case. So is it possible the problem comes from here ? Personaly I don't think.

    - Yes, each power pin of the FPGA is bypassing by a 100nF, you can see that on the schematics, all caps are in SCH_CENT118C-ALIM-OSC_C.PDF and power on SCH_CENT118C-FPGA-AUTOSCH_A.PDF. There are as many caps as power pin. You want I replace all 100nF Vcc FPGA bypass by a 1uF ?