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How are the layers of PMP8372 PCB assigned? Which layer is power ground, analog ground, VEE...?

Other Parts Discussed in Thread: PMP8372, TPS84250, TPS84259

I am working on implementing the PMP8372 as a +/- 3.3V split-rail power solution for a larger system however I am finding the analysis of the Gerber file to be time consuming to say the least. So far, I have followed the top and bottom assembly/layout recommendations exactly except for functional modifications required for the different output voltage (+/- 3.3V instead of the +/- 5V). 

Major questions I hope will be answered:

1. Are top layer copper pours/polygons all that are necessary to provide a ground for the TPS8425x (buck converters) and TPS7Axx (LDOs)?

2. Is it intended for the area I labeled PGND to be connected to a plane layer to be used as clean system ground when this design is used as part of a larger system?

3. Can I connect the equivalent/mirror PGND copper pour of the negative part of the PMP8372 design (not pictured) to the same system ground layer? 

4. Is it recommended to connect the area I labeled as AGND to the ground port of the power jack? Can I connect the AGND copper pour of the negative part of the PMP8372 (not pictured) to the same ground port of the power jack?

I appreciate any help with the above questions.

Thank you in advance!!

  • Hi Menelik,

    1) No, there are 4 internal PGND layers on this board.

    2) PGND is the power ground of your system. This is the common ground connection for VIN and VOUT.

    3) Yes, the TPS84250 and TPS84259 can share the same PGND. I would keep AGND of each device separate.

    4) No, the AGND is the clean ground reference for the internal analog control circuitry. This should be isolated from the switching currents and only connected to PGND at one point (see datasheet). The PGND should be connected to the ground of the power jack.

    If needed you can contact me directly at jarrigo@ti.com. Thanks, Jason

  • Thank you for the reply and further explanation via email.