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LMZ10503 IC getting heated up.

Hi

I am facing an issue with the power IC mentioned in the subject line in my circuit. The issue is whenever I put a load of high current (around more than 300mA) the IC is getting heated up and getting damaged. I have made a 2-layer board. I am sharing the schematics as well as the board file with you. Please let me know if there are any issues in the design and the routing and help me resolve the issue.GNSS RECEIVER FOR MFRS_final_sch_130815.pdfGNSS_RX_FINAL_130815_crl.rar

Thanks

Arnab

  • Hello Arnab,
    I checked your schematic and the component values look alright.
    Can you please send your layouts in a PDF format so that it is easy to review? You could print each layer to a separate PDF page and that'll be perfect. Some suggestions upfront:
    1) Your input bypass cap should be very close to the input and ground pins on the IC. C60 on your schematic seems to be a bulk cap more than bypass. Another 1 uF or 0.47 uF ceramic capacitor right between VIN and GND should be placed. The reason is that without a bypass cap at the input, you can have noise in the system which could impede the proper functioning of the design
    2) Make sure your FB node is very short. You can have a long lead length from VOUT to the top of Rfbt (R65).

    Regards,
    Akshay
  • Hi

    I am sending you the ;ayout details...Please review the same and let me know..

    ThanksGNSS_RX_REV2_190915.rar

  • Any updates? Please respond..

    Arnab

  • Hello Arnab,
    Apologies for the delayed response.
    I looked at your layout and it looks good, but I have a few questions.
    1) Is the IC at the edge of the board and not getting enough copper to sit on? Please make sure you have enough copper area for heatsinking.
    2) On the input side you seem to have a trace going to the input capacitor, but the VIN pins of the IC are on a copper plane. Is there a reason you have so many vias on the input plane? Is the input to the IC coming from bottom layer? On the bottom layer I see a trace coming in to one via which should be on the input plane on the top layer. If that is indeed the trace that's carrying the input current then there could be an issue. Ideally the input plane should be solid as shown on the top and the input current should not be sent through vias. If you can't avoid it then the input trace carrying the current should be fatter to reduce the parasitic line impedance and the current should be sent up multiple vias to cancel the via inductance. It would be helpful if you could explain the vias and the traces on input plane on both the layers.
    3) In addition to that, please send us scope shots of the input and output voltage?
    4) Do you have any good parts/boards? Or are all parts/boards exhibiting this behavior? Have you tried the EVM with your components? How do they get damaged? Is it a blow up or they stop regulating after a certain time? It would help to see some efficiency and input current numbers up to the load that you can manage.

    Regards,
    Akshay