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TPS82085: UVLO threshold test

Part Number: TPS82085

We are using your buck converter TPS82085, and we encountered a problem while testing the UVLO threshold.

We are using the part with the following components:

Input Caps: ceramic 22uF + dielectric 10uF

Ouput Cap: 22uF

FB Resistors: 82.5K between VOUT and FB, 162K between FB and GND (which means VOUT should be 1.2V)

PG Resistor: 499K between VOUT and PG.

At first we used the device with said components, and we saw that while testing the UVLO falling edge threshold, we received a UVLO threshold of 1.9V which is under the minimum value of 2.1V.

After that happened, we tried to remove the ceramic input cap, and remained with the dielectric 10uF input cap, but the result remained the same.

We tried then to remove the dielectric input cap, and remained without any input caps, but the results still remained the same.

Then we also removed the output cap, and we receive a good result of 2.2V falling edge UVLO threshold. Unfotunately, the rising edge threshold was out of spec - a few mV above 2.5V which is the max. value according to the datasheet.

Afterwards we performed the same tests without any periphery components (no caps or resistors), and we tied the FB to VOUT directly. The falling edge threshold was within spec but the rising edge was out of spec. To solve this problem we added an input cap of ceramic 10uF and it solved the problem, but the output voltage was unstable.

Then we returned to the circuit with the periphery components mentioned above. We deducted from the said experiment that the problem is rooted in the output cap. We returned the output ceramic cap of 10uF. The result of the falling edge was good but the output voltage was followed the input voltage until the UVLO, in which the output voltage dropped. 

Do you have any explanation for this behavior?

Thank you

Eli

  • Can you post some waveforms of your measurements? Outside of the IC/EVM, what did your test setup look like?
  • Hi Eli,

    Were you able to resolve this or do you still need assistance?
  • We used the agilent B1500 test equipment.  

    For Vuvlo FALL we started from 3V and dropped to 1.5 V

    Using a gradual decrease in voltage of 5mV with a delay of 50ms.

    In terms of the turn on order, first we connected the ground, then we switched on the Vin and then we increased the voltage to enable 1.5 V when Vout was sampled.

     

    For Vuvlo RISE we started from 0V and went to 3V

    Using a gradual increase in voltage of 60mV with a delay of 150ms.

    In terms of the turn on order, first we connected the ground, then we switched on the voltage Vin and then we increased the voltage to enable 1.5 V when Vout was sampled.   

     

    Thank you, Eli.

  • Thanks Eli for the details. Do you have waveforms of these tests that you can share?

    As well, how do you determine what the UVLO level is? What signal or condition are you looking for?

    Is EN tied to Vin in your testing?
  • Hi,

    I cannot send any pictures from within my organization.

    I determine the UVLO by triggering a rise / fall in the Vout with my agilent B1500.

    The EN is tied to Vin.

    Thank you, Eli.

  • Hmm, it is difficult to debug then.

    You should be able to measure the UVLO levels on the regular EVM in a normal, closed loop fashion. Your Vin ramp speed needs to be slow enough to accurately measure the point at which the IC turns on/off (which is before it starts switching and ramping up Vout). Adding a small (50 mA) load might help better pinpoint the exact threshold on the falling edge.

    Is the UVLO level important in your application? What is your input power source and voltage range?