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HI Allan,

Thanks for offering your help.

First I ll walk you through how I got the waveforms:

1. This is the rectified input from a 24VAC wall transformer:

Here is the data for it:

The 24VAC was rectified by using a full wave rectifier, followed by a 100uF, 10uF, and 1uF bypass capacitors. The schematic does not show the 100uF and 10uF because I added them later adHoc on the board to see if I could it to be more stable.

2. This is what the rectified input looks like when I load the regulator with about 340mA

 Here is the data for it:

So there is some ripple after the regulator gets loaded.

3. Here is the waveform for the 5V regulator output. It starts at 4.98V, and as soon as I load the output with about 340mA the voltage drops to almost 4V

4. Here is the schematic for the power supply

 BTW, I copied the Schematic from the National WEBENCH Power Architect Tool.

I appreciate your help.

Thanks

Hi Gustavo,

I don't see anything obvious from your schematic that points to the problem, though it looks like current limit might be triggering from your Vout screenshot. What is the current rating on the inductor you are using? We can first try to determine if the inductor is saturating and contributing to current limit.

Regards,

Kevin

I am using a Bourns SDR1105 33uH inductor on the output of the 5V regulator.

That is the inductor that the WEBENCH recommended in the design.

Thanks

Hi Gustavo,

It might be a noise/layout issue. Can you please send me the pcb layout? Also, may I have the waveforms at the IS and PGND pins? If this part gets a poor signal from the diode current sense then that would appear as higher current and thus reduce the duty cycle.

Regards,

Kevin

Hi Kevin,

You might be right about the noise. See the attached screenshot. The vpp gets to about 1.5V on the IS pin. What should I be seeing on that pin ?

Here is the layout:

Here is the same Layout but I removed the GND Pour for visibility:

Thanks

Oh, and how would I fix this issue ?

Thanks

Hi Gustavo,

I think if you can reduce the noise on the IS pin, it would help a lot. The voltage on the IS pin will be added to the ramp voltage (240mV for this design), and then compared to the current limit of 2.1V.  Some of the voltage spikes appear up to 1.6V, so the sum of the two is getting close to the limit. The small trace connecting D3 to the IS pin might picking up noise from the SW node, so if you can shorten the trace from the D3 to IS pin on the layout, that might help.

Regards,

Kevin

Hi Gustavo,

Also, improving the ground routing might also clean up the noise, since that is another source of noise. In your layout, it looks like the PGND and AGND are connected to the DAP (which is good), but you might also want to place several vias on the DAP and connect to the ground plane. There are more tips on page 18 of the datasheet: http://www.national.com/ds/LM/LM25575.pdf

Regards,

Kevin