LM2678-12 Voltage drops under load

Hi Michael and Martin,

It is part of the recommended design to add a high frequency bypass capacitor to the input of this switcher. Placing this as close to the IC as possible is essential for keeping high frequency components of the switcher from flooding the GND plane and creating EMI and regulation issues.

I think the issue Martin is seeing is isolated to this bypass capacitor and if placing this across the part solves the issue, there is not much more that can be done from our end.

Michael, what value of capacitance did you choose across pins 2 and 4? Typically it needs to be between 100nF and 1uF, ideally around 500nF or lower. Also can you share your PCB layout? I think this might play a large part into the issues you're seeing since the schematic looks fine.

Additionally, I checked with the product folk and they reported back a nomenclature change but identical process and hence there shouldn't be any cause for worry from fabrication.

Thanks,

Anston

Hi Michael,

Thanks for sharing your layout. I have a few notes to share which will help greatly to optimize design and fix the regulation issues you are seeing.

LM2596 & LM2678

a) The input power (Vin) to these IC's come from Via's that have inductance, coupled with the long traces from the Via's to the Pin and traces to the capacitor, the input of the regulator would experience large ringing. A good solution would be to use polygon's instead of traces and instead of one Via, have multiple Via's bring the power in. The added Via's will act like parallel inductors and cut the inductance in the line. 

b) The Switch node/Ouput Pin is a tricky devil. It demands the inductor be placed as close to the IC and routed with thick and broad traces/polygon. This is definitely a problematic pin if connected to only one Via since the switching cycles play havoc on the parasitics and cause all sorts of problems. Please have several Via's at least 4-6 Via's connected to this pin.

c) The Catch diode must be a schottky with fast recovery and I think you already have this in, however, the diode is Via'd to the inductor or Output node which is not advised. There are over a million cycles of power transfer happening every second between the diode and the output capacitor. In the absence of a direct connection, the parasitic effects are huge. Please place a direct connection (no Via's) between diode and the pin of the IC/or inductor. Also ensure the diode is as close to the IC as possible.

d) I did not find any bypass capacitors in your design. Especially with a two layer board consisting of multiple Via's, and trace connections, please place at least 2 bypass capacitors of .01uF to .5uF for the input and output. Place these caps very close to the IC, to eliminate swtiching noise from propagating through the circuit..

e) The inductor cannot have 5A of current delivered to it through a 1mm trace! Please place a polygon or multiple traces to connect the IC to the inductor. Use minimum 30mils of trace width for every 1A of inductor current considering 1oz copper.

f) For each and every power node, (VIN, VOUT, SW, OUTPUT, CBOOT and GND) please increase the number of Via's from 1 to at least 4-6. They don't need to be as big, but quantity matters. the more the better.

g) You mentioned that the GND plane is absent, so I cannot comment on your GND plane design. But going by placement of the IC's, There doesn't seem to be room for a continuous GND plane between input and output. The GND's seem to Via at one place and pop out the other. The best solution for this is migrating to a 4 layer board with a dedicated GND plane. This might be the culprit behind the less than optimum output regulation.

h) The Boost/Boot capacitor, is connected with a very very thin trace. This simply will not do since there are large switching voltages between the IC and the Boost capacitor. The function of this capacitor is to sustain the Drain voltage on the Top MOSFET so that it is higher than the gate and hence can turn on. This means that every switching cycle there are large voltages created and while your existing placement is ideal, connection to it must be bulked-up.

i) The Boost/Boot capacitor GND is Via'd without any direct connection to the IC GND. This needs to be rectified. Please try as far as possible to provide an in plane GND for diode, boost capacitor and input capacitor. This is absolutely critical.

j) The GND's of the input capacitor and diode need to be very close together.

k) Please place Via's underneath your DAP so as to facilitate better thermals and GND'ing.

Power layout is tricky and very important for correct operation. Please refer to the layout guidelines mentioned in the LM2596 datasheet for further clarification.

If manual routing hasn't been done before, I would highly recommend it for this board. Also, components would need to be rearranged to get optimal routing.

Feel free to contact me for further clarification on anything mentioned above.

Thanks,

Anston