• Resolved

TPS386596: During the power up transition on VDD pin, what's the status of output?

Part Number: TPS386596

Hi team,

I applied a slow voltage rise on VDD pin to deal with the sequence. However, I noticed when the voltage on VDD is rising, output (Reset) pin has a low level output for about 100ms. Is this normal? Thanks.

  • Lanhua,

    If you refer to the timing diagram Figure 1 on page 6, output (Reset) is undefined for Vdd below 0.9V which is called the Power-on reset voltage and is shown as a gray undefined region in the timing diagram. Is that what you are refering too? In terms of how long until the Reset transitions after the Sense voltages come up, that is around 50ms and spec'ed as the RESET delay time in the EC table 6.5.

    Please let me know if I answered your question.

  • In reply to Michael DeSando1:

    Hi Michael,

    Thanks for the reply.

    Yes, I want to know the status during the powering up of VDD.

    My plan was:

    Apply all sensing voltage above the reference voltage before applying voltage to VDD, to avoid the low output. In other words, I don't want to see a low level output anytime unless voltage drop happens after the system starts.

    It seems this will not work since low output pulse has to be generated during power-up even Sense already comes up.

  • In reply to Lanhua Zhang63:


    The /RESET voltage should be low until the device is powered up and SENSE is above the undervoltage threshold. You might see /RESET rising as VDD rises when VDD is below the minimum operating voltage. This is common for these devices and is shown as a gray undefined region in the timing diagram of Figure 1.

    A work around solution to keep /RESET low until the device powers up is the 2 transitor solution we came up with:

    This circuit will keep /RESET low until the device powers up in which /RESET will go high when SENSE is above the UV threshold.