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Part Number: TPS386596
I applied a slow voltage rise on VDD pin to deal with the sequence. However, I noticed when the voltage on VDD is rising, output (Reset) pin has a low level output for about 100ms. Is this normal? Thanks.
In reply to Michael DeSando1:
Thanks for the reply.
Yes, I want to know the status during the powering up of VDD.
My plan was:
Apply all sensing voltage above the reference voltage before applying voltage to VDD, to avoid the low output. In other words, I don't want to see a low level output anytime unless voltage drop happens after the system starts.
It seems this will not work since low output pulse has to be generated during power-up even Sense already comes up.
In reply to Lanhua Zhang63:
The /RESET voltage should be low until the device is powered up and SENSE is above the undervoltage threshold. You might see /RESET rising as VDD rises when VDD is below the minimum operating voltage. This is common for these devices and is shown as a gray undefined region in the timing diagram of Figure 1.
A work around solution to keep /RESET low until the device powers up is the 2 transitor solution we came up with:
This circuit will keep /RESET low until the device powers up in which /RESET will go high when SENSE is above the UV threshold.
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