I am interested in the behavior of the watchdog timer immediately following the de-assertion of the RESET following power-on. In looking at the timing diagram supplied on page 10 of the specificaiton, the watchdog timer input (WDI) is a don't care during the interval where the RESET is asserted following power on (e.g. VDD > Vit). However, what is not shown is the state of the internal watchdog timer once the RESET signal goes high. Does the watchdog timout start only after RESET turns off? Put another way, how soon after the de-assertion of the RESET signal much the first assertion of the WDI input occur?
The watch dog timer begins when the RESET signal initially goes HIGH at startup. This was verified in lab.
Please click the Verify Answer button on this post if it answers your question. Thanks!
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