TI E2E Community
Supervisor and Reset IC
Supervisor and Reset IC Forum
TPS3808 timing capacitor question
The tps3808 datasheet indicates 1.25msec = 100pF capacitor. However, the equation on page 9 indicates a 1.25msec delay would be a 131pF cap.
The minimum time-out specified is 1.25mS and the smallest timing capacitor is specified as 100pF. The electrical characteristics page shows 100pF since this is the extreme in capacitor choices. The time-out using a 100pF still falls within the range shown in the table. The equation is the linear interpretation of the graph shown in Figure 4. You can see in Figure 4 that there is a change in slope of the graph around 1nF. The time versus capacitor value graph becomes slightly non linear for small values of capacitors which is giving the small difference in calculated capacitor values.
I had a customer ask a similar question. I used your answer for first pass reply.
However, it sounds like they are wanting to quantify any errors with respect to the delays. Do we have any approach to quantify the errors in delay?
First question would be silicon alone, then what would the contribution be from capacitor tolerance.
My first reply indicated to use the graph, then apply the tolerance from capacitance from the equation.
My first reaction, is that they are trying to use this device with more precision that design intended. Could you comment?
Unfortunately (as usual), they are on a short fuse and would like answer ASAP.
We don't individually quantify the error terms for the delay. The aggregate error is reported as the min/max values. The min/max values do not include the tolerances of external componenets (such as the timing capacitor tolerance and temperature coefficients). You are correct that this must be added on top of the the range shown in the datasheet. Generally speaking, voltage supervisors are not meant to be precision time circuits but are only meant to generate a reset for a microcontroller. If they are worried the reset signal is too short, then the usual solution is to increase the nominal reset time. The only impact is the microcontroller stays in reset a few exta milliseconds.
Is there any data that could be used to bound the delay for a specific capacitance/vcc value?
I think they are trying to bound the min/max range for their specific conditions. Not sure how much of an influence the large VDD range has on the variability of the delay.
No, we only characterize the total error due to all factors.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.