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TPS3823 Watchdog question

Mitchell Kary
Intellectual 630 points
Other Parts Discussed in Thread: TPS3823

Hello,

I am designing in the TPS3823-33QDBVRQ1 to act as a watchdog timer and wanted to verify operation after power-up and before the processor boots up and toggles the WD pin. During the boot process the WD pin will be held high. Can I assume that the TPS3823-33's reset output will remain active high after VCC increases past VIT- threshold and stay there until the first transition of the WD pin. Is it this first transition at the WD pin which starts the watchdog timeout?

Thanks,

Mitch

  • 0
    TI__Guru 55940 points

    Hi Mitch,

    Not exactly.  First, the /RESET will only go high after VDD exceeds VIT- + hysteresis.  The watchdog timeout will be active from the time that /RESET goes high.  The timer is reset for the first time on the first transition of WD.  In order to disable the watchdog, WDI should be floated.  Here is an App Note that describes a quick circuit that can be used:

    http://www.ti.com/lit/an/slva145/slva145.pdf

    One other thing that should be noted is that if you are using a non-A version of TPS3823, if the processor has a possibility to transition WDI while /RESET is low, an external N-Channel FET is needed to ensure proper operation.  More information on this topic can be found on page 2 in the datasheet.

    Very Respectfully,

    Ryan