TPS3813 Datasheet 5-page Timing Diagram

Hi Kazu,

Good question. The timing diagram for a window watchdog supervisor can be a bit complicated as there are multiple fault conditions. The fault conditions that will set RESET/ low are: (1) Vdd is below the minimum supervisor voltage, Vit, (2) a WDI pulse is received too soon after another WDI pulse, (3) a WDI pulse is not received or received too long after another WDI pulse. I've gone through more detail below:

The shaded area on RESET/ refers to when the output is not defined as you are below the minimum voltage for the device to be able to ensure RESET/ is in a known state.
 The shaded area for the WDI signal refers to the lower boundary for the watchdog timer window. If a second WDI pulse is received in the shaded area, RESET/ is pulled low. The size of this window is user-determined, as per the table on page 8 which calls it the lower window frame.

Onto the timing diagram, the below outlines the timing diagram:

When Vdd is initally below 1.1V, RESET/ is in an unknown state. As Vdd ramps from 1.1V to the threshold, Vit, RESET/ is held low as the power supply is not fully established for you system. Once Vdd goes above Vit, RESET/ goes high, after the set delay tme td, and starts the first watchdog window. The first window has no lower boundary.

The rising edge of the first WDI pulse resets the internal timers and starts the second window, with a lower boundary based off of the first window. This is to ensure that the WDI logic is based off of the timing of WDI signal. The second and third pulse on WDI are correctly received within the window, so RESET/ is high.

The fourth pulse on WDI is below the lower boundary for the window, as it comes up in the shaded area. This pulse has arrived too soon and as such RESET/ is sent low to signal the fault condition. After the delay time td RESET/ goes high again and a WDI pulse is correctly received.

RESET/ than goes low again as there is a brownout on Vdd and Vdd falls below Vit. Vdd than rises above Vit and after a delay time, td, RESET/goes high and the watchdog timer is waiting for the first rising edge within the upper window boundry.

The next two WDI pulses are correctly recieved so RESET/ stays highs. The system is than powered down so RESET/ goes low as Vdd goes from Vit to 1.1V, and below 1.1V the RESET/ signal is in an unknown state.

Regards,

David

David-san,Thank you very much for your explanation.
I didn’t know that RESET/low was set when WDI pulse is received in the shaded area of the lower boundary.
Best Regards,Kazu Ogawa

Hi Kazu,

Good to hear and just let us know if you have any more questions. We are always happy to help.

Regards,

David