Customer design following circuit.
※Vsense:①+5.0V、②+3.3V、③+4.5V
⇒Vth:①+4.5V、②+2.9V、③+4.2V
【Problem】
Though the Vsense voltage of everything exceeds Vth (5V or 3.3V), a reset signal is a condition of "Low".
Is there a mistake in a circuit diagram?
(Are MR, CT and Watchdog OK?)
Please let me know.
Best regards,
Satoshi