TPS3823-33 weird behavior

Gordon Su

Other Parts Discussed in Thread: TPS3823

Hi,

i am using TPS3823-33 non-A version on my board. i noticed from datasheet and other questions on this forum that i am not allowed to toggle WDI when RESET_N is asserted. otherwise, RESET output will remain asserted. i have some questions on what will happen if i stop WDI toggling.

this is what i see on my bench. upon power on WDI starts toggling and RESET_N pin stays LOW. when i manually disable WDI toggling RESET_N pin goes HIGH after Td duration. so far this is what i am expected. however, RESET_N stays at HIGH regardless my subsequent attempt to manually enable and disable WDI toggling. it is as if the watchdog IC does not function at all. is this expected behavior? please advise.

delay and timeout duration in the datasheet is only spec at room temperature. can you also provide the numbers over temperature range?

Gordon

over 9 years ago

0 Martin Sulzinger over 9 years ago

Prodigy 50 points

Hi Gordon,

you said "attempt to manually enable and disable WDI toggling" does that mean, you disconnect the WDI line manually?
That is the same behavior I encountered here:
e2e.ti.com/.../1461999

So I assume you disconnected the WDI-line by instering a jumper or something, and after disconnecting your WDI pin is left floating. This does disable the watchdog functionality of the device. After disconnecting WDI, try connecting a pull-down resistor to the WDI pin.

Regards
Martin

0 Gordon Su over 9 years ago in reply to Martin Sulzinger

Intellectual 285 points

not really. I used a CPLD to generate pulses to WDI input. i manually asserted reset to CPLD. WDI input is driven LOW when CPLD is being reset.

0 David Hopkins over 9 years ago in reply to Gordon Su

TI__Expert 8905 points

Hi Gordon,

That does sound unusual - could you please provide a schematic?

Regards,
David

0 Gordon Su over 9 years ago in reply to David Hopkins

Intellectual 285 points

Hi,

please see below the schematic. CH1_WDOG is driven by CPLD. when reset to CPLD is asserted manually CH1_WDOG is driven LOW. otherwise it is being toggled.

0 David Hopkins over 9 years ago in reply to Gordon Su

TI__Expert 8905 points

Hi Gordon,

We are looking into this problem and are going to bench test it.

Regards,
David

0 Gordon Su over 9 years ago in reply to David Hopkins

Intellectual 285 points

looking forward to your update.

0 David Hopkins over 9 years ago in reply to Gordon Su

TI__Expert 8905 points

Hi Gordon,

I was not able to replicate your failure - in fact I saw the opposite. If WDI stops toggling you will time out the RESET/ once, after which RESET will stay high. When you reconnect your WDI signal and time it out again the RESET/ will go low, as expected. I did learn however that this device generates its own WDI pulse and that to disable the internally generated WDI you need to pull down WDI - if you think this is the problem I would advise a 4.7kOhm pull-down on WDI based on my results.

I am posting scope shots of this on the original of these TPS382x postings here:
e2e.ti.com/.../1461999

Regards,
David

0 Gordon Su over 9 years ago in reply to David Hopkins

Intellectual 285 points

you are right. I realized that CPLD tri-stated TPS3823 WDI input instead of driving it LOW. I am still trying to figure out why. CPLD behavior does not RTL.

Thanks for trying to duplicate the issue. appreciate it.

Gordon

0 David Hopkins over 9 years ago in reply to Gordon Su

TI__Expert 8905 points

Hi Gordon,

Not a problem and I am happy to help.

Regards,
David

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TPS3823-33 weird behavior