TPS386000 use. How much time the RESET signal is asserted?

Hi Bob,

After a fault is detected,  /RESET will remain low for the time delay (td) after the sense line returns above the threshold.  The reset delay time can be programmed as described in the RESET DELAY TIME section of the datasheet.

Very Respectfully,

Ryan

Dear Ryan,

Thank you very much for reply.
I'm sorry late for reply.

May I ask a add question?

I think that "td time" is until RESET signal deasserted.

My customer want to know RESET asserted time.

I have attached file.

Best regard.
Bob Lee.

Have a question at TPS386000_151016.pdf

Dear Ryan,

Could you update me the progress?
I will need to update the customer on the progress.

Best regard.
Bob Lee.

Dear Ryan,

Could you update me, the progress of last week?
I need to complete the reply until the Oct 30.

Best regard.

Bob Lee.

Hi Bob,

My apologies for the delay.

Td is the time delay from when SENSE crosses the threshold in the positive direction and /RESET goes logic high.

The time for /RESET to go to logic low (when SENSE crosses the threshold in the negative direction) is dependent on the overdrive. Please refer to Figure 14 in the datasheet for the overdrive curve. The minimum pulse width is the time delay for the SVS to transition /RESET from logic high to logic low.

Very Respectfully,
Ryan

Dear Ryan Eslinger,

Thank you very much for reply.
My customer answered your reply.

Best regard.
Bob Lee.