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TPS3852: SET1 input performance

Jeffrey Cranmer
Intellectual 630 points
Part Number: TPS3852
Other Parts Discussed in Thread: TMS570LS0232, TPS3890

I require a little clarification of the data sheet for the TPS3852.

When we have a watchdog fault, this will initiate a PORRST event on the TMS570LS0232, since my WDO output is wire-or connected to the output of a 1.25V monitor IC connected to the power-on reset pin of the microcontroller.

Figure 20 of the datasheet shows a typical application where the SET1 input is connected to a TPS3890, which generates a long input pulse to disable the Watchdog timer during reset recovery / power up initialization. This circuit will work well for intial startup, but the concept fails when you have a watchdog induced reset, since you no longer have a disabled watchdog for the second initialization period.

One possible fix for this would be to feed back the watchdog induced reset to the /MR input pin of the TPS3890.  This would disable the watchdog by clearing the SET1 input low to repeat the initial power up reset watchdog event.

My question is, what happens to the \WDO output if SET1 is cleared low during the 200ms nominal WDO low pulse period?  Does the WDO output immediately go high impedance, or does the tRST delay complete before the \WDO pin goes into the high impedance state requested by SET1 low?

Or do I need to use nRST warm reset instead, and initiate watchdog recovery code which immediately services the watchdog once it comes out of reset?

  • 0
    Intellectual 630 points
    Also, the data sheet states:
    "7.3.4.5 Watchdog Output WDO
    The TPS3852 features a window watchdog with an independent watchdog output (WDO). The independent
    watchdog output gives the flexibility to flag when there is a fault in the watchdog timing without performing an
    entire system reset. For legacy applications WDO can be tied to RESET. While the RESET output is not
    asserted the WDO signal will maintain normal operation. However, when the RESET signal is asserted the WDO
    pin will go into a high impedance state. This is due to using the standard RESET timing options when a fault
    occurs on WDO. Once RESET is unasserted the window watchdog timer will resume normal operation."

    Is this true for RESET asserted only by the device, or is it also true if another system asserts a RESET event at the WDO output (e.g. if I tie the /WDO output to nRST and nRST is pulled low by an internal system interrupt)?
  • 0 in reply to Jeffrey Cranmer
    TI__Expert 6825 points

    Hi Jeffery,

    If SET1 is pulled low disabling the part /WDO will go high impedance and will go logic high. If the SET1 pin is not kept low longer than trst, /WDO will remain high until the trst has been completed. If this behavior is not desired force a /RESET (forcing VDD below VIT-) to clear this.

    Section 7.3.4.5 Watchdog Output /WDO is talking only about /RESET and /WDO events issued by the TPS3852. If an external device issues a /RESET both /WDO and /RESET will maintain normal operation. If the TPS3852 issues a /RESET, /WDO will go high impedance until trst has expired.

    Let me know if you need anything else for this.

    Regards,

    Mark

  • 0 in reply to Mark Sellers
    Intellectual 630 points

    Hi Mark.  

    My apologies, but I still need a little clarification on the reaction of the part to a change in status of the SET1 input.

    Please can you confirm that this interpretation is correct.

    1. If SET1 is pulled low before a WDO reset event is triggered, then
      1. the watchdog function is disabled immediately,
      2. WDO goes high impedance, and
      3. The WWDT will be disabled until the state machine is reset, 150us after SET1 returns high.
    2. If SET1 is pulled low during a WDO reset event, then
      1. the full WDO low pulse (time = trst, nominal 200msecs) will complete before WDO goes high impedance.  
      2. Immediately upon expiration of the trst output pulse,
        1. the watchdog function is disabled,
        2. WDO goes high impedance, and
        3. The WWDT will be disabled until the state machine is reset, 150us after SET1 returns high.

    Thanks

    Jeff

     

  • 0 in reply to Jeffrey Cranmer
    TI__Expert 6825 points

    Hi Jeff,

    I appologize for any confusion I created with my last response. I have attached a scope capture that should help clear this up. This scope capture shows what happens when the WWDT is disabled during its reset event.

    I coppied your post below so I can answer your qeustions one by one.

    Jeffrey Cranmer said:

    Hi Mark.  

    My apologies, but I still need a little clarification on the reaction of the part to a change in status of the SET1 input.

    Please can you confirm that this interpretation is correct.

    1. If SET1 is pulled low before a WDO reset event is triggered, then
      1. the watchdog function is disabled immediately,
        1. Yes, this is correct if SET1 is pulled low before a WDO reset event the watchdog function is disabled and inputs to WDI are ignored.
      2. WDO goes high impedance, and
        1. Yes WDO will be high impedance and the pullup resistor should try to bring it high.
      3. The WWDT will be disabled until the state machine is reset, 150us after SET1 returns high.
        1. If SET1 is pulled low before the WDO reset event it will be disabled until 150us after SET1 returns high. Unless there is another fault on the RESET line, this will cause WDO to remain high impedance until that is cleared as well.
    2. If SET1 is pulled low during a WDO reset event, then
      1. the full WDO low pulse (time = trst, nominal 200msecs) will complete before WDO goes high impedance.
        1. No disabling the watchdog timer will cause WDO to go high impedance. See the attached scope shot. SET1 is in pink, WDO is in blue, and RESET it in yellow.
      2. Immediately upon expiration of the trst output pulse,
        1. the watchdog function is disabled,
          1. The watchdog is disabled as soon as SET1 is pulled low.
        2. WDO goes high impedance, and
          1. WDO goes high impedance as soon as SET1 is a logic low.
        3. The WWDT will be disabled until the state machine is reset, 150us after SET1 returns high.
          1. Correct WWDT will be disabled until SET1 returns high. In the scope shot I have attached you can see that when SET1 returns high WDO remains high for ~63ms (twdu), this is because there is no WDI signal input to the WWDT. Thus, when the upper boundary is exceeded WDO will be pulled low for 200ms.

    Thanks

    Jeff

    Regards,
    Mark