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TPS3510: Problem with Vdd

Part Number: TPS3510

Hello,

I am using component TPS3510 in one of my project and I have a problem for the Vdd pin. Does my Vsb has to be 12V or it can be something else ? What are the diodes values ?

If it is 12V, isn't there a problem with PGI after since max value for PGI is Vdd+0.3 but <7V ?

If I could have some more information on how it works that would be perfect :)

Thanks for your help

Thomas

  • Thomas,

    Thank you for choosing our device! What is your problem with Vdd? I will try to answer all your questions.

    Vsb can be any voltage within the Vdd supply voltage provided in the EC table: 4V to 15V but the overvoltage threshold for Vdd is set for 13.8V (typical).

    The diodes have a 0.5V drop across them and provide a little cushion so a 12V supply at Vsb will appear as 11.5V at the Vdd pin. This means the device won't trigger overvoltage condition until the Vsb reaches 13.8V (typical) + 0.5V diode drop = 14.3V. The diodes can be altered as necessary.

    There is no problem with the PGI when Vsb = 12V since the external resistor divider should be chosen to divide Vsb down so that the voltage at the PGI pin does not exceed "Vdd + 0.3V with max = 7V". The resistor divider should divide Vsb down so that the trip point (output of the resistor divider going to PGI pin) of your chosen Vsb is 1.15V (typical).

    How this device works: depending on what voltage you want to monitor (3V, 5V, 12V) you will either use VS33, VS5, or Vdd respectively. If using Vsb other than 12V, you will either need to use an external resistor divider, diode, or come up with another way to make sure the voltage at the Vdd pin is between 4V and 15V. When the voltage at Vdd is above 13.8V (typical) for more than 73us, the FPO output goes high and PGO goes low. PGI needs to be set up so that the voltage at PGI pin (coming from Vsb and divided down) is above the undervoltage threshold of 1.15V and not above 7V in any case. If the undervoltage condition is met at PGI or VS33 or VS5, the PGI pin goes active (drops low) which causes PGO pin to go active (drops low) and FPO goes active (latched high). If overvoltage is met at VS33 or VS5 or Vdd, the PGO pin goes active (drops low) and FPO goes active (lactched high). For undervoltage detection to be turned on and working, PSON needs to be active (low). For specifics about timing, see the datasheet.

    I hope this helps you! Please let me know if you have any more questions or need clarification and I will do my best to help. Thank you!

    -Michael

  • Hello,

    Your answer is perfect !
    I understand better now

    Thanks a lot for your help !

    Thomas
  • Hello Michael,

    Does this schematic seems correct to you ?

    Best regards

    Thomas

  • Hey Thomas,

    After reviewing your schematic, I believe your resistor divider (R40, R41) needs to be reversed meaning R40 and R41 need to be swapped. This current configuration sets PGI pin to 10.5V which is much higher than the abs max for this input.

    Everything else looks good!

    -Michael