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TPS386000: WDI is not impact the RESET1

Part Number: TPS386000

Hi team

  My customer is using TPS38600 for monitor the FPGA, schematic as below, and lately we found that if WDI keep low or high, the WDO won't reset the MR and keeps high, so whether WDI has or not, the WDO not functional, so I'm wondering if you can review the schematic and give us some comments.

  and in datasheet block diagram, the WDI is connected to RESET1, but didn't explained in datasheet.  

  • Randy,

    To reset the processor by WDT time-out, WDO can be combined with RESET1 by using the wired-OR with the TPS386000 option. For legacy applications where the watchdog timer time-out causes RESET1 to assert, connect WDO to MR; see Figure 35 for the connections and see Figure 6 and Figure 7 for the timing diagrams. By connecting /MR to /WDO, when the WDI causes /WDO to trigger which then causes the device to reset, the device holds the status with the internal latch circuit. To clear this time-out status, a reset assertion of RESET1 or RESET is required meaning a negative pulse to MR, a SENSE1 voltage less than VITN, or a VDD power down is required.

    WDI should not be connected to RESET1. Does the customer connect WDI to RESET1 in their application?

    -Michael

  • Hi Michael

      Thanks for the comments.

      I tested the board today and found there's another 3.3V input to MR/, and it's through 22ohm, so the WDO/ and MR/ should be low, but the 22ohm pull up resistor is too small that affected the pull down. The waveform show as below: CH1 is the WDO/ MR/, CH2 is the RESET1.

      

     So i changed the input resistor to 3k, then the RESET1 really is 600mS reset the FPGA, but the WDO/ and MR/ is always high. I think the WDO/ and MR/ should be the same with RESET1, right? but it seems TPS38600 internally reset when watch dog timer time out. Waveform as below: CH1 is RESET1, CH2 is WDO/ and MR/

      

    So I'm wondering if you can give us some comments based on above tests, thanks. 

  • Randy,

    The TPS386000 provides open-drain reset outputs. Pullup resistors must be used to hold these lines high when /RESET is not asserted, or when RESET is asserted. The pullup resistor should be no smaller than 10 kΩ to ensure the safe operation of the output transistors. By using wired-OR logic, any combination of RESET can be merged into one logic signal but if separate pull-up resistors are used for each RESET output then the resistors should be similar value.

    In the schematic, R22 is the /MR pull-up resistor and looks like its 47kohm which is good. But your scope captures suggest the pull-down strength for /MR and /WDO is not strong enough. Can you confirm the pull-up resistor values?

    -Michael

  • Hi Michael

      They have two inputs for the MR/, one is the WDO/ pull up 47k to MR/, another is logic 3.3V with series 22ohm resistor to MR/, so the 22ohm actually too small for the pull up. This is the waveform I referred to the first waveform, it's because MR/ can not be reset, so the watch dog function is kind of disabled. 

      Then I changed this 22ohm to 3k, then the watch dog timer is good now, but as you can see the second waveform, the reset time seems too long referred to the datasheet you mentioned, and the RESET1/ or WDO/ is not getting low when time out. it seems it's internally reset the RESET1/, not outside.

      Is there anything not clear? thanks. 

  • Randy,

    The 3k should be higher like at least 10k and should actually be the same at the 47k for wired OR logic. The resistor should be in the open-drain configuration, not in series, so that the node can be pulled high or to ground depending on the state of the device.

    -Michael