Hi team
My customer is using TPS38600 for monitor the FPGA, schematic as below, and lately we found that if WDI keep low or high, the WDO won't reset the MR and keeps high, so whether WDI has or not, the WDO not functional, so I'm wondering if you can review the schematic and give us some comments.
and in datasheet block diagram, the WDI is connected to RESET1, but didn't explained in datasheet.