Other Parts Discussed in Thread: TPS3850
Hi all,
in our design we are trying to use the TPS3813K33DBVT as clock monitor in order to verify the presence of a 25Mhz3.3 LVCMOS Clock connected to the WDI input.
The goal is that if the input clock is not present the open drain output should be mantained at low level.
I tryed all the four basic possibilities by connecting WDR and WDT to GND and VDD respectly but I Always see the output resetting periodically...with different period depending from these pins.
Is possible to perform this task with this device?
If is not possible can you suggest me if there is a device with same package to perform this task?
Any suggestions?
Regards
Alberto