TPS3823: auto-reset oscillator

Kanji,

I'm not sure I understand. There needs to be a signal on WDI at least 100ns wide and occurs at least once every 1.6 seconds otherwise the device will reset. Since you are using the A version (TPS3823A), the input to WDI will still be active even when reset is asserted. The A version does not latch the reset signal to the asserted state if a WDI pulse is received while RESET is asserted.

The customer also doesn't need the switch? The reset output can only be pulled high is connected to the pull-up resistor. If the switch opens the reset output, the reset output might not function correctly.

Does my answer help you?

-Michael

Dear Michael san

Thank you for your quick responce.

I was sorry my poor English .

Please let me explain the customer's question again.

>There needs to be a signal on WDI at least 100ns wide and occurs at least once every 1.6 seconds

>otherwise the device will reset.

=>

Yes.

The Internal Auto-reset oscillator is  once every 1.6sec also?

>Since you are using the A version (TPS3823A), the input to WDI will still be active even when reset is asserted.

>The A version does not latch the reset signal to the asserted state if a WDI pulse is received while RESET is asserted.

=>

Yes, in case /RESET=L, and WDI is active, /RESET stuck low in case null version.

Customer's question is not in case /RESET=L , but /RESET=H.

Customer think Auto-reset oscillator is available ,so /RESET keep High   when  input to WDI  is Hi-Z (CPU is standby). Its okay.

In transition from CPU standby to active, customer's CPU may pull WDI terminal to low .

There are probability that  the pulse of Internal Auto-reset oscillator which is once every 1.6sec ,  and  the transition timing ( CPU pulls WDI low) duplicates by chance.

So,in that case WDI pulse ( by internal osc)  may distinguished.

The transition detecter/watchdog timer logic ( data sheet p10) may loose the toggle pulse.

So, /RESET may asseted low. once.

So, to prevent this, customer added analog switch to keep  /RESET=High in case transition from CPU=standby to active.

I would like to have your opinion again if available.

Best Regards

Kanji,

The Internal Auto-reset oscillator is  once every 1.6sec also?

-Yes.-

Customer's question is not in case /RESET=L , but /RESET=H.

Customer think Auto-reset oscillator is available ,so /RESET keep High   when  input to WDI  is Hi-Z (CPU is standby). Its okay.

-Yes, correct-

In transition from CPU standby to active, customer's CPU may pull WDI terminal to low .

-This is ok. WDI will think this is a pulse-

There are probability that  the pulse of Internal Auto-reset oscillator which is once every 1.6sec ,  and  the transition timing ( CPU pulls WDI low) duplicates by chance.

-This is ok. You can have more than one signal occur every 1.6 seconds but AT LEAST ONE must occur.-

The transition detecter/watchdog timer logic ( data sheet p10) may loose the toggle pulse.

So, /RESET may asseted low. once.

-Why would the watchdog timer lose the toggle pulse? The toggle pulse must keep pulsing at least once ever 1.6seconds.-

So, to prevent this, customer added analog switch to keep  /RESET=High in case transition from CPU=standby to active.

-Problem with switch: if switch is OPEN and pull-up resistor is DISCONNECTED from /RESET, the reset will be floating. /RESET needs pull-up resistor to be pulled high.-

Question:

When you remove the switch, does the /RESET stay low when CPU transitions from standby to active?

-Michael

Dear Michael -san

Thank you for your answer quickly!

Customer is still designing their circuit using TPS3823 so they did not captured yet actual /RESET =low by WD timeout from  CPU mode change.

I think /RESET deos not stay low continuously  because after delay time "td" (200ms typ), /RESET go back to high.

Also, as you mention, if internal auto-reset osc keeps pulsing, WD timeout  will be cleared next time, and /RESET will not stay low.

Customer's concern is not /RESET stays low continously, but /RESET (may) goes low once in case mode change of CPU ( But not captured yet). 

Anyway thank you for your support.

Best Regards