TPS3838: TPS3838 issue - Trying to drive a low pulse from a CPLD and TPS3838 seems to be driving high

Hi Jeff,
Can you please provide additional details on the VDD supply rail and what is the RST pin connected to. Also it would be good to capture the scope image for the pulse and the reset signal.

Thanks
Chintan

Here is the circuit. I was trying to pulse this line from the CPLD low, but couldn't do it (didn't see it on the scope). I can drive it low, but looks like when I try and generate a pulse for about 200ns, I don't see it.

Once I lifted the pin to the 3838 part, I can now see  the pulse.

Thanks,

Jeff

Jeff,

I can't see the circuit. The /RESET for TPS3838 will go low when the VDD voltage drops below the V_IT voltage spec or if /MR is pulled low. The propagation delay from when VDD drops below the negative-going input threshold voltage V_IT and the /RESET pin actually going low is 50us max. VDD also needs to below the threshold for 6us before the /RESET to trigger in the first place. When the VDD returns above the threshold, the device delays before releasing the /RESET to the normal high condition. 

Can you tell me more about the 200ns pulse? Is the /RESET suppose to go low for 200ns then back high? Please try to attach the circuit so I have a better understanding of the connections. Thanks!

-Michael

Sorry, I am having a hard time attaching (or pasting something). Can you help?

Click "Use rich formatting" on the bottom right corner of the box. This should open up a message with more features so you can attach items. Do you see that button?

-Michael

I do. That is what I tried. I pasted the picture in and I saw it, but when I hit post it was gone

Matty,

Please send to my email for further assistance.

michaeldesando@ti.com

-Michael

Matty,

The open-drain /RESET output will go low only if VDD drops below the VIT threshold for longer than 6us or if /MR is pulled low for longer than 1us. If /RESET does go low, it will stay low for the delay time after either VDD comes back above the VIT threshold or /MR is pulled back high. The delay time will depend on your CT pin configuration.

You mentioned "It looks like I am unable to drive a low pulse after power up from the CPLD.. For some reason, I believe that the TPS3838 is preventing this from happening. I can drive it low from the CPLD for a long time, just not a pulse."

1. How are you attempting to drive a low pulse, are you using VDD or /MR pin on the TPS3838 device?
2. Your pulse can't be shorter than the minimum pulse to trigger the /RESET to go low plus the delay required before /RESET is released back high. What pulse are you going for and what time are you seeing?

-Michael

I am trying to drive it low from my programmable device (CPLD). I have MR pulled high to VDD during this.

I have waited the 200ms or so after RST goes high to try and drive this signal. I had it tied to a counter so I was able to vary the pulse width to what I wanted.

Once the RST pin was pulled from the TPS3838 device, I was then able to drive it low.