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TPS3850-Q1: TPS3850-Q1:About WDI input timing when WDT is enabled

Part Number: TPS3850-Q1
Other Parts Discussed in Thread: TPS3850

I want to check the WDI timing when the WDT changes from disabled to enabled.

Figure 1 on page 7 of the TPS3850-Q1 datasheet shows the timing diagram.
The following contents are described in this figure.
・WDI input timing after reset deassertion. (t < tWDU)
・WDI input timing for second and subsequent times after reset deassertion. (tWDL < t < tWDU)

For example,
 1)Set SET0 = 1, SET1 = 0 to disable the WDT.
 2)Set SET0 = 0, SET1 = 0 to enable the WDT.
 
In this case, which is the correct timing for WDI input?
 a)t < tWDU
 b)tWDL < t < tWDU

-Harukawa

TPS3850-Q1_WDI timing.pdf

  • Noritomo,

    Please see Figure 3 in the datasheet. When watchdog is disabled then enabled, there is a special setup delay to setup the watchdog called t_WD-setup. Once the setup delay passes, then it goes to case (a) in which the time must be t < tWDU.

    For more detailed information, read section 7.3.5.1.1 Enabling the Window Watchdog and also see Figure 26.

    I hope this answers your question! Let me know if anything is unclear.

    -Michael