BQ2205LY: BQ2205LY

Hi Eduardo

The RST pin is dual function. It will generate a reset or it can be used to reset the device with an external button press.

Figure 2 shows the “generated” reset. Basically, the device backs up an SRAM with a coin cell when the main power supply (VCC) drops below VPFD. It holds it low – potentially preventing the controller from trying to do something as power fails or before it fully recovers. It holds the RST pin low for tRST after VCC recovers.

CE (SRAM Chip Enable) is the input to the device and CECON is the “conditioned” CE. Figure 2 also shows CECON as VCC fails. Actually CECON1 and CECON2 for 2 SRAM banks if needed. Table 1 shows the Truth Table of CE/, A (address or bank selection pin), CECON1 and CECON2. As noted earlier, if power fails, the CECON pins are high.

As an input, if the push-button is held low for “tPBL” (Push Button Low) then the bq2202LY will hold the RST pin low for an additional tRST which will generate a reset for the system. Note that a very small push button (1µs) can generate a “long” 30ms to 85ms pulse on RST.

In no cases will the RST function (internal or external) impact what’s going on in the CECON pins. So, RST will NOT impact the memory.

When memory is corrupted, it’s usually one of a few issues.
1. The slew rate on VCC is too fast (see tF). Add more capacitance to VCC.
2. Pins going below ABS max (-0.3V). This can cause all sorts of issues, but mainly it can cause loss of data. Cause of this can be poor ground, poor isolation or a variety of other issues. Possibly floating RST with a negative spike?

Quick problem identifiers:
A. Check VCC slew rate on failing supply.
B. Check all pins for negative undershoots.
C. Pull RST high.

thanks
Onyx