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TPS3808: MR/n rise time

Part Number: TPS3808

MR/n is a logic input with Vil <= 0.3*Vdd and Vih => 0.7*Vdd

Would there be an issue in adding an RC delay for the rising edge of the MR/n pin (say, 4.75K to Vdd and a 0.1uF cap, 475usec time constant)?

The concern is that the slowly rising input would draw excessive supply current or cause some other problem.

Also, if the MR/n pin sees "chatter" such a switch bounce, does the reset output time restart?

  • Steve,

    There is no issue with adding RC delay filter to /MR pin. Note: that if you pull /MR to GND with RC delay filter, it could take some time for the capacitor to discharge as well. That is the only concern I could see but not a big concern at all. And the /MR pin requires a pulse width of 0.001us in order to cause a reset. This spec is provided in table 7.6 Switching Characteristics table.

    Please let me know if you have any other questions. Thanks!

    -Michael