MR/n is a logic input with Vil <= 0.3*Vdd and Vih => 0.7*Vdd
Would there be an issue in adding an RC delay for the rising edge of the MR/n pin (say, 4.75K to Vdd and a 0.1uF cap, 475usec time constant)?
The concern is that the slowly rising input would draw excessive supply current or cause some other problem.
Also, if the MR/n pin sees "chatter" such a switch bounce, does the reset output time restart?