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TL7700: TL7700 response time at power supply down detection (falling)?

Part Number: TL7700

Dear support member,

My customer used TL7700.

I have a question.

Would you teach the response time of the reset signal at power supply down detection (falling)?

I attacheded file about question.

Could you check it?

Best regard.
Bob Lee.

TL7700 question.pdf

  • Bob,

    The response time of the reset signal at power supply down detection falling is defined by "Propagation delay time, SENSE to Output" t_pd spec which is 10us max. The time it takes for the output line to fall (slew rate of the output line) is 0.5us max.

    Please let me know if you have any other questions. Thanks!

    -Michael

  • Dear Michael,

    Thank you very much for reply.

    May I ask a question?

    Datasheet description is stated that CT = 0.01μF and tpd = 10μs, tf = 0.5μs,
    but also is the same time at CT = 2.2μF?

    Best regard.
    Bob Lee.

  • Bob,

    Yes, CT does not affect the falling propagation delay. This is because when VDD is falling, the internal FET turns ON and pulls the output "low" internally and the internal FET will short out CT so that it has no impact on the timing. CT only affects the rising output since this is when internal FET is turned OFF and the output rises according to the CT delay.

    -Michael
  • Dear Michael,

    Thank you very much for reply.

    I reply my customer your answer.

    I will feedback it.

    Best regard.
    Bob Lee.

  • Dear Michael,

    I will feedback about my customer situation.

    My customer was very grateful.
    Thank you very much.

    May I add a question?

    I have a question about reset signal delay time (tpo) at power supply establishment.

    Datasheet description is stated CT=0.01μF, tpo=0.5ms, 1ms, 1.5ms.


    Q1
    Why are there existence minimum and maximum times?


    Q2
    Is there information on the time variation of tpo when the capacity of Ct changes?
    For example, when the capacitor changes with DC VIAS, is there a time variation in tpo?


    Best regard.
    Bob Lee.

  • Bob Lee,

    A1:
    The min and max times are provided because the internal current source that charges the delay capacitor can vary slightly from device to device due to device tolerance. This spread follows a Gaussian distribution with most of the devices performing with typical specs meaning the internal current source is about 2.5uA charge current. But some devices might have slightly higher or lower charge current so this will slightly changes the delay time. In some of our newer devices, we really work on tightening this timing spread for better timing accuracy but in this device, TL7700, the spread is +/- 0.5ms for CT = 0.01uF.

    A2:
    Yes. In section 8.3.3 in the Datasheet, you see the t_po equation. When CT value changes due to DC bias or temperature or capacitor tolerance, you can measure the actual value of capacitance and input into the equation to find the typical delay time.

    Does this answer your questions? Please let me know if you have any more questions.

    -Michael
  • Dear Michael,


    Thank you very much for reply.

    May I add question?

    Q1
    CT affects the rise time, but is there how to calculate Output rise time Tr time?

    Q2
    The same question as tpo,
    Is there information on the time variation of Output rise time Tr when the capacity of Ct changes?


    Best regard.
    Bob Lee.

  • Bob Lee,

    A1. Please refer to section 8.3.3 in datasheet for equation that sets reset delay. The delay is the time required for the internal current source to charge up the delay capacitor to the internal reference voltage. The equation is:

    t_po = Ct x 10^5 seconds where Ct is the delay cap in Farads

    Also see Figure 6 in the datasheet for the typical output pulse duration vs timing capacitor curve.

    A2. Rise time doesn't change where as the delay time does change when Ct value changes. The rise and fall times are fixed based on design.

    -Michael

  • Dear Michael,

    Thank you very much for reply.


    My question was not communicated well.


    My question about this time is,
    Output pulse duration time is not.
    Output rise time is.


    Q1.
    Does Output rise time slope with CT capacitor?


    Q2.
    Is there information on the time variation of Output rise time Tr when the capacity of Ct changes?

    Best regard.
    Bob Lee.

  • Bob Lee,

    A1.

    The rise time and fall times do not change with changing capacitor. Only the moment the rise time begins can be delayed with the capacitor. Does this answer your question?

    A2.

    No variation of output rise time. We only provide a max value for this spec which covers all device variations.

    -Michael

  • Dear Michael,

    Thank you very much for reply.

    I reply my customer your answer.

    Also, I wii feedback my customer situation.

    Best regard.
    Bob Lee.

  • Thank you for your response.

    I am working with "Bob Lee 62837", he is an engineer and I do customer's Q&A support.

    I talked with the customer about this matter and the situation was as follows.

    The slew rate of the RESET signal doesn't fluctuate with CT capacity, but in the past there were the following answers.
    (We and the customer don’t discuss this answer because we can not confirm who sent this answer in the past.)


    The figure above is a composite of the TL7700's internal and peripheral circuits.
    ① The comparator output of Q1 and Q2 becomes the current of Q4.
    ② To make the current of Q4 zero, it is necessary to set the collector current of Q2 to zero.
    ③ This assumes that the comparators Q1 and Q2 become Q1: ON, Q2: OFF, but a voltage difference of about 50 mV is required for Q1 and Q2.
    ④ Therefore, if slew rate of CT is loose, it takes time until this voltage difference occurs, during which Q5 also turns ON and the slew rate of RESET signal becomes loose.

    Is this consider correct?

    if this consider is correct, does the slew rate of RESET signal depends on CT capacity?

    Best regards,
    Masumi Sekiguchi

  • Masumi,

    I can't confirm the internal schematic you provided since I have not seen this before and it does not match what is provided in the datasheet. Since TL7700 is an open-collector output topology, a capacitor on the /RESET output so only affect the slew rate when /RESET signal is "low" and going "high" since the capacitor on the output will need to charge thus slowing down the slew rate of the output signal. But when the /RESET output is "high" and goes "low", the capacitor will be shorted out and thus has no effect. Please let me know if this agrees with your thinking. Thanks!

    -Michael
  • Since it is not necessary to reply to this post, please reply below.
  • Pokkun,

    I will post the same reply I posted on the other forum.

    The only information we provide related to the CT pin and delay is the current source current which is 15uA typical. The actual equation depends on the current source current, and the voltage threshold that the cap charges to. But the datasheet provides an estimation in section 8.3.3

    delay = Ct x 10^5 seconds where Ct is the capacitance in farads



    Please also refer to Figure 6 in the datasheet which shows the delay vs timing capacitor.

    Let me know if you have any more questions. Thanks!



    -Michael