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TPS3808: Vdd applied - reset response with regard to the timer

Part Number: TPS3808

What does the RESET timing diagram look like when the Vdd is applied long after the Vsense pin is applied.

Case 1: The Vsense is above the threshold as Vdd is applied

Case 2: The Vsense is below the threshold as Vdd is applied

Is the reset still delayed by the timer programming value?

Are the timer programmed values maintained in this situation? (20msec, 300msec, programmable)

  • Steve,

    When the VDD is off and then applied, the device will then follow the delays spec'ed in the datasheet once the Vdd reaches the power-up reset voltage which is 0.8V.

    Case 1: when Vsense is above Vit, then Vdd comes up past 0.8V, the delay will be t_d (reset delay time) which will depend on the configuration of CT.

    Case 2: When Vsense is below Vit, then Vdd comes up past 0.8V, the delay will be t_pHL (high-level to low-level reset delay) which is ~20us typ. Before Vdd reaches 0.8V, the output could be rising. So the /RESET output will fall to 0V once Vdd passes 0.8V and this timing will be close to t_pHL.

    Yes the reset is still delayed by the timing capacitor on the case where Vsense is above Vit. The timer programmed values should be maintained with possible variation due to the time won't start until Vdd reaches the value for RESET to be defined which is 0.8V. This means that there could be slightly longer delays due to the start-up condition. If the slew rate of the VDD is very slow, the time it takes for VDD to reach 0.8V should be ignored when measuring the "delay".

    -Michael