• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 62 subscribers
  • Views 701 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS3705: Reset pulse from watchdog fault

Mark Guastaferro
Genius 11095 points
Part Number: TPS3705

My customer indicates that he is seeing a 9us reset pulse coming from the RESET pin when the device detects a watchdog timeout.  WDO output is responding properly, but our understanding is that the RESET output should not be impacted by the watchdog event. 

Is this expected behavior? What external event could be causing this?

  • 0
    TI__Genius 11095 points
    Additional information:
    There are two circuit versions with this supervisor that shows this issue. On one board with a direct connection between WDO and the processor, there is a 1.5s delay from when WDO goes low and the RESET pulse starts. On another board which has a 10K resistor in series between WDO, this delay is 3.5s.
    About 100 ns after RESET goes back high, WDO returns high. This part makes sense since RESET being low will make WDO go low.
  • 0
    TI__Genius 12630 points
    Mark,

    The Reset delay for this device is 200ms, and under no condition, should the delay be 9us. Can you provide oscilloscope captures showing the VDD, /MR, /RESET, WDI, /WDO pins?

    This will help us see what is happening and help determine the cause of the issue.

    -Michael
  • 0 in reply to Michael_DeSando
    TI__Genius 11095 points
    Hi Michael,
    I'm trying to get the waveforms, but I think you misunderstand what I described. The RESET delay is not 9 usec. This is the width of the RESET pulse that is seen during a watchdog timeout event. The problem is that there should be no RESET low event during an active WDO timeout as long as the VDD voltage is maintained above the reset threshold.
  • 0 in reply to Mark Guastaferro
    TI__Genius 11095 points

    Hi Michael,

    Attached are some waveforms on this issue.  These show the WDO and RESET outputs in response to a watchdog time out. In these, you can see that the RESET output goes low for about 9 usec after the WDO has been low. The interesting thing is that the WDO output goes back high about 100 nsec after the reset goes low. I suspect the WDI signal is returning high at the point the reset goes low and WDO goes high shortly after this. Since a 9 usec RESET pulse is not possible,  this must be either an internal glitch from the WDI signal, or some kind of coupling in their circuit to the reset pin.

    I have asked for the WDI waveform, but don't have it yet.   

    tps3705 Reset investigation.docx

  • 0 in reply to Mark Guastaferro
    TI__Genius 12630 points
    Mark,

    I see the issue now. This is not an issue we have seen before. We might need to start the customer return failure analysis process. Some questions to determine if it is the device or the board/configuration:

    1. How many units has this issue been observed on? Does this issue occur every time or sometimes?
    2. Has a known-to-be-working device been used?
    3. Is this a new application or an application that at one point has been working without issues?

    If any information is sensitive, feel free to contact me directly at michaeldesando@ti.com

    -Michael
  • 0 in reply to Mark Guastaferro
    Guru 140200 points
    Hi Mark,

    this could be caused by a noisy PCB or an improper layout. Does the PCB contain a solid ground plane? Are the decoupling measures proper?

    Can you catch narrow noise spikes on the chips's pins with the scope?

    Kai
  • 0 in reply to kai klaas69
    TI__Genius 11095 points
    We found that the processor was pulling the reset line down because of an internal reset. There is no issue with the operation of the TPS3705. This post can be closed.