TPS3802: The rise time of Vdd

Hi Takahiko,

the /reset output shall go down to 0V as fast as possible when VDD is below the nominal value. But when VDD is going above the threshold value the /reset output shall wait the delay time before going high. Does the chip work like this in your application?

Kai

Hi Kai-san

Thank you for the reply.
The /reset output is high without delay time before Vdd excceding Vth.
This problem occurs only first power activation.

Best regards,
Yokota

Yokota,

Before VDD reaches 1.1V, the RESET output is undefined and can ramp as high as 0.2V while VDD is powering up. Is this what you see? Please provide oscilloscope captures to show the issue. Thanks!

-Michael

Hi

TPS3802.pdf

Hi Takahiko,

is the /reset line driven by the output of another chip at the same time?

Kai

Hi Kai-san

No, the /reset line isn't driven by the output of another chip at the same time.

Best regards,
Yokota

Yokota-san,

I don't see any issue. This is a push-pull device meaning when VDD is above the VIT threshold, RESET pulls high to VDD. As you increase VDD, the RESET "high" voltage will continue to increase also since RESET = VDD when VDD > VIT. I can see the moment when RESET pulls high right after the initial slope on RESET signal.


-Michael

Hi Michael,

the TPS3802 provides a /RESET signal, not a RESET. So, during power-on, after VDD has reached 1.1V the /RESET signal should go to 0V and stay there for 380ms before going high.

Kai

Kai,

You are correct. I misread the signal.

Yokota-san,

Can you provide a schematic of the application? Is anything connected to the /RESET pin?

-Michael

Hi Michael-san

Thank you for the reply.
The schematic is customer's confidential information, so I can't attach the schematic.
May I send it you by e-mail?

Best regards,
Yokota

Hi Michael-san, kai-san

I affirmed that condition to my customer.
There were the potential that reset terminal of CPU was high logic because latch-up occured as power on sequence to CPU.

Best regards,
Yokota