Hi
Can you clarify what do you mean by " , do we need to decoupling it?edge connects to the CPU output and during reset can change at least once at the reset wdiWDI pin may be active (transitioning high and low) when the TPS3820/3/4/8 is asserting RESET" ,in the typical application
, do we need to decoupling it?edge connects to the CPU output and during reset can change at least once at the reset wdiWDI pin may be active (transitioning high and low) when the TPS3820/3/4/8 is asserting RESET" ,in the typical application
I assume you are asking about the wording in the Description paragraph on page two of the datasheet. This means that you can NOT apply a changing WDI signal to the TPS3820 if the IC is in reset. You must disconnect the WDI signal to the IC when /RESET is low. If you apply a changing WDI signal when /RESET is low, the /RESET pin can latch low even if VDD goes above the threshold to pull the IC out of reset.
Note the existing question about the TPS3820 WDI pin.
http://e2e.ti.com/support/power_management/svs_and_sequencers/w/design_notes/tps3820-watchdog-question.aspx
Hi Michael
Thanks for the feedback
Not clear what do you mean by the pin can latch low , do you mean latch for ever?
My concern is that in typical application when the wdi input connects to a CPU IO output on the reset edges the wdi signal might change, can this lead to an ever reset state?
Yes, latch low forever until you disconnect and reapply power to the IC.