In the case of momentary loss of power, is there a minimum time for Vdd to be below the threshold in order for the device to resume normal function when power is restored?
What I am seeing is a momentary dip in Vdd (from 3.3V to about 0.4V), which returns to its normal value after about 200ms. After this, RSTVDD never goes high after MR deasserts (plus time delay). Attached is a screen capture indicating this condition. SENSE and RSTSENSE are not used.
Please adivse when you can - thanks.0044.TPS3106.doc
Thank you for recording the issue. We are currently looking into this. Do you also have a circuit schematic on the applicaiton?
Schematic is attached.
I am unable to replicate this in lab as you can see from the waveforms 1030.D013.TIF .
However, on page 14 of the datasheet, it mentions that if you expect transients on the MR pin (like the waveform you have attached) it is best to connect a diode from MR to VDD. On the waveforms you attached, when the 3.3V rail turns back on, I see a slight spike on MR. Having a diode will definitely limit the MR/VDD voltage difference. In addition, the section dicusses having a 0.1uF capacitor from MR to gound in noisy environments.
Just for clarification, can you indicate which signals are associated with the respective traces on your plot?
Trace 1 (Orange) = RESETVDD
Trace 2 (Green) = MR
Trace 3 (Red) = VDD
VDD goes low for about 200ms then goes back up. At this time, MR is low and comes up about 100ms after VDD, and RESETVDD pulls up about 100ms later.
Can you run your test again, but keep the MR signal high when Vdd is reduced? This will more accurately simulate conditions atr this end. I am curious whether something is latching up (for example) that is preventing the RESET signal from clearing when normal conditions are resumed.
Let me know if and when you can try this - thanks again.
Sorry - more input from me. The drop in Vdd is not a step function, but really an R-C discharge. Are you using an arbitrary waveform generator to run this test? If so, then perhaps changing from square (pulse) to triangle wave will be a closer simulation to conditions here.
Also, will the part operate differently if Vdd is not driven all the way to zero (as it was in your case)? For example, if Vdd drops to 400mV, what is its behavior when Vdd is restored? What if it only drops to 1V?
Next, what if the low Vdd condiion exists for less time (example, only 100ms)?
Thanks again for your assistance.
MR must be less than or equal to VDD as stated in the datasheet. I confirmed this is the lab and RESETVDD does indeed stay LOW if this condition is violated. Placing, a diode between MR and VDD easily fixes this.
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