The TPS3838 is an active low reset open drain supervisor; as such it is possible (and often desirable) for other circuits to be paralleled (wire OR'ed) on the /RESET output.
I would like to understand if the internal reset in the TPS3838 comes into play when another circuit drives the /RESET signal low? For example if a short glitch pulls the /RESET low for some short period of time (e.g. a few ns) will this trigger the internal timer and result in the /RESET line remaining low until the timer expires.
The datasheet doesn't describe the TPS3838 timing behavior when an external circuit pulls the /RESET low.
Thanks in advance for providing this insight.
The real reason for using the open drain configuration is, as you say, so that these /RESETs can be paralleled. The internal /RESET circuitry is sufficiently isolated from the output such that anything external that pulls down that pin will have no influence on the function of the IC and will not trigger any of the its' reset responses.
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