I have question for operating reset function of TPS3813
so i would like to know for detail operating sequence of Vdd, RESET, and WDI
1. if WDI input of TPS3813 continue to low, reset is no come out?
2. otherwise if Vin come in, reset is come out repetitively fixing to WDI input pulse?
customer want to device such as from special point driving WDI input triggering
Please explain for operating method of TPS3813
Someone will support shortly. Please remember when you make the forum subject to put the IC name first, followed by a short description of the quesiton. This one woudl be something like "TPS3813 - RESET and WDI
Please refer to the timing diagram on page 5 of the TPS3813 datasheet:
During startup, RESET is LOW until VDD reaches VIT. After a delay TD, the TPS3813 waits for a WDI transition (rising or falling edge). This initiates a window-watchdog based on how WDR and WDT is configured (see page 8 of the datasheet). RESET will go LOW if there is no WDI transition inside the window; in other words, there must be a WDI transition inside the window for RESET to stay HIGH. If the WDI transition is before the window (gray area) then RESET will go LOW then go HIGH until there is a WDI transition. Then another window-watchdog is made and so on.
Please let me know if my understanding of the customers two conditions is correct.
1) During this condition, is VDD on or off? First priority is VDD because it powers the watchdog. VDD must be above VIT, otherwise RESET will stay LOW.
2) When VDD is on, the IC will operate as described above depending on your WDI input.
Please clarify what the customer is seeing. Possibly with attached waveforms. Thanks!
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