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Hello, I'm working up an application of the UCD90120A. We have 10 rails, and for starters we just want to
sequence them all up and generate a "power good" on a GPO to fire up a Xilinx XC7Z020. That is to say,
no voltage monitoring. We have assigned Pin 17 (GPIO5) as our "Power Good" line to the Xilinx.
What's the best way to have pin 17 come up with ONLY a fixed delay (no other dependencies)?
If you assign Pin 17 as GPO, monitor the rails' "Power Good", then Pin 17 will be asserted whenever the voltages on the rails that it monitor >= the Power Good voltage set for these rails.
When you assign Pin 17 as Logic GPO, the state of the pin depends on the logic that you set for that pin. Depends on your configuration and your intention, then set the logic so that it is always true.
In reply to Anne Ngo77:
Hello Anne, I just wanted to thank you for your response. We figured it out and finished things up fine.
The device will be flying in space actually, suffice it to say. It's being used to monitor and sequence an
Thanks again, Marcus
In reply to Marcus Perry:
In reply to Lalit Kumar4:
The below app note may give you a quick start.
In reply to Zhiyuan Hu:
Thanks for the reply. Actually i'm using Auto Mode for enabling Sequence for FPGA. I just wanted to know whether Enable pin will work as an output or not?As i told you earlier i want to give a sequence through my UCD90120a chip. Since i'm not able to configure Rail as an output to particular pin og FPGA and also not able to get what should be the initial dependency for that rail. Kindly help me or send me some code for understanding that.Regards,Lalit
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