Do you have an estimate of the propagation delay from the instant PMBUS Control is de-asserted externally to when the UCD90160 will de-assert the enable signal on the first power rail (assuming TOFF_DELAY=0 and ignoring the external capacitance on the EN line)? Is this logic flopped or is it purely combinatorial logic?
In my system it is critical that I control power down sequencing but the only advanced warning I receive is when the input 12V rail starts to droop. So I have a very small window from when I detect 12V below some threshold (say ~10V) and when the 12V rail reaches the limit of the secondary regulators (~6-7V) in order to sequence my rails down (I don't have the ability to place a huge cap on my board to survive longer so I need to shutdown quickly). My plan is on power loss to put the board in a low power state immediately and kill all non-essential rails right away. So I'm hoping to get an estimate of how long it will take to de-assert the initial non-essential rails.
Also, is there a way to speed up the ADC monitoring of the key rails during power down? If I only have ~3 rails that have shutdown dependencies can I assume that the cycle time of the ADC is only 3.89us * 3 in this situation? Or does the ADC always cycle through all rails even if they are not dependencies for the shutdown? Alternatively, can I rely on the accuracy of the TOFF_DELAYs in this situation (ex: 200us will be +/-20%) to sequence down the rails (assuming I hard shunt the rails appropriately externally)?
Thank you!
Josh