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UCD90160 where are status/faults written?

Hi,

This is what I am trying out:

 

1. Setup the watchdog config(D3), using pmbus/i2c via the processor in uboot/linux.

2. Reset it via watch dog reset (D4) in linux.

3. Stop the reset and have the board reset.

 

Read the status post reset and determine the cause to be due to watch dog reset.

 

Steps 1, 2 and 3 are done.  

 

However on reading the status (be it MFR_STATUS 0xF3 or logged faults 0xEA) post reset, the watchdog reset bits are not set and your help in this area is needed. Please clarify the following:

 

> Is the status/faults written in the RAM? Does resetting the chip  reset the RAM?

> If so, is there a way one can read the faults/status post reset?

Thanks,

  • The System Watchdog Timeout fault is logged in flash (NV memory). You should be able to read it from EAh. But if the log is full, no new fault will be logged. You can enable FIFO mode to allow old log to be overwritten. You also need to give enough time for the device to finish logging (several millisec) before resetting the device.

    In STATUS register, System Watchdog Timeout fault is bit 11 of MFR_STATUS.  The STATUS register is in RAM. RAM will be lost after resetting the device. No way to recover RAM after reset. All you have is the fault log in flash.

  • Thanks for the fast response Zhiyuan.

    Is there a recommendation on how many millisec does one need to provide to the device for a successful log, prior to reset?
  • Best to wait for 300ms to let device finish all flash operation. 80ms is minimum to keep a valid log.