Hi,
This is what I am trying out:
1. Setup the watchdog config(D3), using pmbus/i2c via the processor in uboot/linux.
2. Reset it via watch dog reset (D4) in linux.
3. Stop the reset and have the board reset.
Read the status post reset and determine the cause to be due to watch dog reset.
Steps 1, 2 and 3 are done.
However on reading the status (be it MFR_STATUS 0xF3 or logged faults 0xEA) post reset, the watchdog reset bits are not set and your help in this area is needed. Please clarify the following:
> Is the status/faults written in the RAM? Does resetting the chip reset the RAM?
> If so, is there a way one can read the faults/status post reset?
Thanks,