The data sheet specifications are for a 10 nF cap between the Tadj pin and ground. I need a smaller clock cycle though. How low can i go? What are the tradeoffs in reducing the Tadj capacitor value?
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The data sheet specifications are for a 10 nF cap between the Tadj pin and ground. I need a smaller clock cycle though. How low can i go? What are the tradeoffs in reducing the Tadj capacitor value?
Kenneth,
Please see previous E2E post that answers this question. https://e2e.ti.com/support/power_management/svs_and_sequencers/f/212/p/208795/740859
We are working to verify the calculations and simulations in lab. Let me know if you have any questions.