LM3881 Sequener - how small a clock period can I get, i.e., how small a capacitor value can I put between the Tadj pin and ground

Kenneth Aquino

The data sheet specifications are for a 10 nF cap between the Tadj pin and ground. I need a smaller clock cycle though. How low can i go? What are the tradeoffs in reducing the Tadj capacitor value?

over 7 years ago

0 Michael_DeSando over 7 years ago

TI__Genius 12630 points

Kenneth,

Please see previous E2E post that answers this question. https://e2e.ti.com/support/power_management/svs_and_sequencers/f/212/p/208795/740859

We are working to verify the calculations and simulations in lab. Let me know if you have any questions.

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LM3881 Sequener - how small a clock period can I get, i.e., how small a capacitor value can I put between the Tadj pin and ground