UCD90160 - Capacitiance on PMBus pins

Amanda Ross95

Hello there,

I'm curious to understand what the Trise and Tfall spec that each of the following pins can sustain without interfering with normal operation?

PMBUS_CLK
PMBUS_DATA
PMBUSALERT
PMBUS_CNTRL
PMBUS_ADDR0
PMBUS_ADDR1

For PMBUS_CLK and PMBUS_DATA, the datasheet says 120 ns maximum in order to stay within operating parameters but it does not specify this for PMBUSALERT or PMBUS_CNTRL. I also checked SMBus Spec and it only calls out Tr and Tf for CLK and DATA signals as well. Would you be able to provide some insight?

Thanks so much!

-Amanda

over 7 years ago

0 Fery Feng over 7 years ago

TI__Intellectual 2270 points

Hi Amanda,

The maximum capacitive load of PMBDAT and PMBCLK pin is 400pF. And the maximum Tf and Tr for Data and Clk is 300ns, minimum for 20ns.
There is no specify value for alert and control pin.
For ADDR0 and ADDR1, just keep no capacitance in these pin.

Thank you.

0 Amanda Ross95 over 7 years ago in reply to Fery Feng

TI__Intellectual 2740 points

Thanks so much!

0 Amanda Ross95 over 7 years ago in reply to Fery Feng

TI__Intellectual 2740 points

Is there a recommeneded capacitance that should be placed near the PMBus pins? If so, what value?

0 Brad over 7 years ago in reply to Amanda Ross95

TI__Genius 13700 points

Do not add any capacitance to the PMBus lines.

The goal is to minimize the capacitance.

Think of the RC time constant between the pull-up resistor and the bus capacitance and what would happen to the Clk/Dat edges with increasing capacitance.

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UCD90160 - Capacitiance on PMBus pins