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UCD90160: UCD90160 not enabling the power rails once powered off [Cold condition board]

Part Number: UCD90160

Hi

We are using the UCD90160 in our design to monitor the voltage rails and perform the voltage rails sequencing.

I am facing the below issue in the design:

"We programmed the UCD90160 with the correct power rails sequencing & conditions and stored the program in UCD90160 internal memory. All power rails are properly worked and validated fine.

All power rails are turned up once board is cooled i.e. after 3 hours in power off condition. Board power rails will come once after warming up the board again for few minutes."

Please let us know your suggestions.

Thanks

Pench

  • Hi Pench

    Could you please describe your problem more clearly? what kind of problems are you facing here? if there is a project file, please share it on the forum?

    Thanks

    Yihe

    1. Issue statement

      When the board is powered with the 12V DC, observed +0v85_1,+1v8_1,+1v2_1,+0v6 and FPGA1_VTTREF Voltage rails generation issue and TI sequencer UCD90160 is not generated the corresponding enable signals.

      Requirement:

      Ultrascale SoC power-on sequence scheme: +0v85,+0v9,+1v2,+1v8,+2v5,+3v3,+5v0, +0v85_1, +1v8_1,+1v2_1,+0v6 and FPGA1_VTTREF.

      Observation:

      +0v85_1, +1v8_1,+1v2_1,+0v6 and FPGA1_VTTREF Voltage rails generation issue observed after +5v0 generation with TI Sequencer program with the multiple rail Turn-on dependencies.

      Analysis-Root cause:

      +0v85_1 enable signal not generated to the GE power module after +5v0 generation with the TI Sequencer program with the multiple rail Turn-on dependencies. Positive response seen by doing the TI Sequencer program with single rails Turn-on dependency [As implemented in the AC701 Evaluation Board for the Artix-7 FPGA EVM].

    2. Attached final sequence program is correct to meet the Ultrascale SoC power sequence requirement?Final.zip

  • Hi Yihe,

     

    Please find the issue summary below:

     

    1. Issue statement

      When the board is powered with the 12V DC, observed +0v85_1,+1v8_1,+1v2_1,+0v6 and FPGA1_VTTREF Voltage rails generation issue and TI sequencer UCD90160 is not generated the corresponding enable signals.

      Requirement:

      Ultrascale SoC power-on sequence scheme: +0v85,+0v9,+1v2,+1v8,+2v5,+3v3,+5v0, +0v85_1, +1v8_1,+1v2_1,+0v6 and FPGA1_VTTREF.

      Observation:

      +0v85_1, +1v8_1,+1v2_1,+0v6 and FPGA1_VTTREF Voltage rails generation issue observed after +5v0 generation with TI Sequencer program with the multiple rail Turn-on dependencies.

      Analysis-Root cause:

      +0v85_1 enable signal not generated to the GE power module after +5v0 generation with the TI Sequencer program with the multiple rail Turn-on dependencies. Positive response seen by doing the TI Sequencer program with single rails Turn-on dependency [As implemented in the AC701 Evaluation Board for the Artix-7 FPGA EVM].

    2. Attached final sequence program is correct to meet the Ultrascale SoC power sequence requirement? 

    Regards

    Pench

     

  • Attached final sequence program6303.Final.zip

  • This post has been answered.
    The reason is that the POWER_GOOD threshold of the 5V rail is set higher than what POL outputs.
    Thanks
    Yihe