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LM3881: LM3881 open-drain flag outputs: need to be 0 upon power up

Part Number: LM3881

I need to sequence a power up system and I find the LM3881 ideal.

The flag signals are used to enable / disable DC/DC converters. Those signals must be active high, which means that upon power up, they must be 0.

The point is: how can this be possible if the flag signals need to be pulled-up? Im using the same rail to power the chip and the flags pull-ups.

Thanks

  • Alfonso,

    The way the LM3881 operates is that when the EN pin goes high on the LM3881 device, the FLAG 1, 2, 3 signals will then go high after a specifc delay time set by the CADJ capacitor. The FLAG pins are low when the EN pin is low because because the internal FETs inside the device are turned on which causes current to flow from the supply voltage through the pull up resistor on the FLAG pin through the internal FET to GND which pulls FLAG to GND thus it is low. When EN is high, the internal FETs turn off which causes no current to flow from supply voltage through pull up resistor so there is no voltage drop across the pull up resistor so the FLAG output will be high. You can use the same rail to power the chip and the flags using the following configuration:

    Please let me know if you have any more questions! I hope this helps!

    -Michael

  • Hello Michael,

    My doubt is: what happens at time t=0? The input supply has just come to its nominal voltage. If the flag outputs are open-drain, they need to have a voltage applied to their gate in order to produce a 0 at the drain. Arent there glitches or strange effects in the flag lines?

  • Alfonso,

    At t=0 the flags are low. There is a delay of about 2.4 ms between EN going high and the flags going high so even if you power up the device and EN, the flags will remain low until the delay has expired. The delay help ensures no glitches and can be extended by increasing the Cadj capacitor value. You can get different delay sequences and delay times by contacting TI for a special business case. When the voltage comes up on the power, this is applied to the open drain gate which causes the open drain output to remain low until the Cadj capacitor discharges which then causes the output transistor to turn off causing the output to go high which is how the Flags go high. There are no glitches or strange effects due to the well designed internals of the device. I hope this helps :)

    -Michael