• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 62 subscribers
  • Views 1118 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCD90120A: Minimum pulse width on GPI to trigger logged fault?

Jonathan Bender
Expert 7895 points
Part Number: UCD90120A

Hello,

I have a signal connected to pin 39 (TMS/GPIO22), and the pulse duration is 600 us.


Is there a minimum pulse duration specification for GPIs to ensure the signal is always captured and logged as a fault?

I couldn't find a spec in the datasheet. The below note in the Fusion GUI mentions that there may be a GPO pass-through delay of up to 1 millisecond if using a non-optimized GPI pin mapping, but no mention of the minimum width of the input signal itself.

Thanks,

Jonathan

  • 0
    TI__Guru 58060 points

    Hi Jonathan

    Non-optimized GPI is polled(not interrupt) based on the system loading, therefore the min pulse duration varies.

    600us would works most time, but 1ms is more safe for sure. if this system is critical, it is highly recommended to use optimized GPI.

    Regards

    Yihe

  • 0 in reply to yihe
    TI__Expert 7895 points
    Hi Yihe,

    Thanks for the reply. So it looks like for the optimized GPI mappings, the minimum pulse width is 100 us, and for the non-optimized, it's 1 ms.

    I couldn't find mention of the optimized mapping in the datasheet, but using the GUI warnings, it appears to be the following for UCD90120A. Can you verify that only these specific GPI mappings will have the 100 us minimum pulse duration detection?

    GPI #1 - Pin 11 (GPIO1)
    GPI #2 - Pin 12 (GPIO2)
    GPI #3 - Pin 13 (GPIO3)
    GPI #4 - Pin 14 (GPIO4)
    GPI #5 - Pin 25 (GPIO13)
    GPI #6 - Pin 33 (GPIO16)
    GPI #7 - Pin 34 (GPIO17)
    GPI #8 - Pin 35 (GPIO18)

    It appears the above order and mapping is fixed. So if I only have 7 assigned GPIs in my system, I can't have GPI #7 be Pin 35 (GPIO18) and still get 100 us minimum pulse duration on that input. Is that correct? Or is there any other possible order / pins / combination?

    Thanks,

    Jonathan
  • 0 in reply to Jonathan Bender
    TI__Guru 58060 points
    Hi Jonathan
    Yes, the mapping is fixed. GPIO18 has to be the 8th GPI to get fast responses. what are the 7 GPIs? can they be re-arranged to achevie this?
    thanks
    yihe
  • 0 in reply to yihe
    TI__Expert 7895 points
    Hi Yihe,

    Thanks for the confirmation. Will make sure to use this mapping in the future if sub-ms fault logging / response is critical.

    The signal in question can be adjusted for a longer pulse width, so for this particular design, will do that instead of physically changing the schematic.

    Jonathan