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UCD90120A: False Rail Disable

Part Number: UCD90120A

Hello,

I'm seeing a strange issue where the enable line for one of my power rails is deasserting for 300-400 µs then reasserting itself.  It is the last rail in the sequence.  With the logic I have loaded on the power monitor, there are only two ways that should cause the enable line to deassert.

  1. There is a fault on any of the other rails.  This is not happening as far as I can tell.  No faults are logged, and the only fault response I have is to shut down immediately without restart.
  2. The PMBUS_CNTRL line is deasserted.  I have probed this line and it does not appear to be deasserting.

My question is thus: Is there any other logic internal to the power monitor that could cause the enable line to deassert without power rail fault or PMBUS_CNTRL going low, or is there a possible bug in the device that could cause such a glitch?

Below is a scope shot of the Enable line in pink and the corresponding rail voltage in yellow.  My interpretation is as follows:

  1. The enable line deasserts for a short period (~400 µs).  There was no overvoltage or undervoltage issue and the rail is within the power good thresholds.
  2. Once the enable line reasserts, the regulator has to go through its softstart process again, so the voltage continues to droop.
  3. The power monitor sees that the voltage is below the power good threshold (2.25 V) and deasserts the enable line again, causing the rest of the regulators in the system to desequence.


If I lower the POWER_GOOD_OFF threshold to about 1.5 V, the regulator is able to recover, but the enable line continues to drop repeatedly (see image below).

  • If the PMBUS_CNTRL line is very briefly deasserted then reasserted, could that cause the behavior described?
  • If the nRESET line is very briefly deasserted then reasserted, could that cause the behavior described?
  • Once a desequence is initiated, can it be halted and reversed?

Thanks very much for your assistance.

-Stephen Bennett

  • Hi Stephen
    Could you please share your project file? I want to check to make sure there is no incorrect settings.
    EN will not change itself until some events are present, fault, pmbus_command, PMBUS_CONTROL, nReset.
    Was this only present on the EN signal of last rail?

    Did any signals out of UCD90120A indirectly control the nReset/PMBus_CTRL signal?

    Could you please probe the PMBUS_CTRL, nRST along with EN to make sure there is not glitch on these. otherwise, what you observed could be expected.

    Regards
    Yihe
  • It turns out it was a noise issue on the PMBUS_CTRL line - we had it white wired in and it was picking up noise.  Twisting a ground around the line resolved the false rail disable issue.

    Thanks,
    Stephen Bennett