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TPS3828-33 (etc) datasheet: decoupling WDI with an N-channel FET

Steve Fairhead
Prodigy 30 points
Other Parts Discussed in Thread: TPS3828

Seems to me the datasheet is all kinds of wrong with respect to this FET. As drawn, I just can't see how it could work.

The FET source is connected to the WDI pin, while the gate is driven by /RESET (so that the FET is off in RESET). Finally the watchdog kick signal is applied to the drain. For this to work, the source (WDI) must be maintained at a low level, with a low impedance, at all times. The WDI isn't low-level low-Z - accordingly to the block diagram, it's fed from an internal oscillator through a 40k resistor. Therefore the FET won't ever be on, and the watchdog will never trigger. Indeed, this is exactly what we find in practice.

Am I missing something, or is this a datasheet typo? Clearly the gate-source threshold voltage is unspecified, but even then I can't see how it would make any difference.

Steve

  • 0
    TI__Mastermind 36110 points

    I agree that this is a less than ideal solution.  I believe this will work for you if  your WDI signal is less than your /RESET voltage.  For example, if your FET has a threshold voltage of 1V, then you will need to make sure your WDI signal is 1V higher than your /RESET signal so the FET's gate to source voltage (/RESET to uP GPIO output) is greater than 1V.

  • 0 in reply to Matthew Day
    Prodigy 30 points

    >> I believe this will work for you if  your WDI signal is less than your /RESET voltage. <<

    That's down to the device, not me. The datasheet implies that it's weakly pulled-up/down to an internal oscillator, and that the current (max 190uA) is *into* the device. So the WDI pin is relatively high impedance, and certainly not a low-impedance low voltage.


    Steve

  • 0 in reply to Steve Fairhead
    TI__Mastermind 36110 points

    I should have clarified my statement better.  I meant to say that I believe this will work for you if your microprocessor generates a watchdog signal that is at a lower voltage than your /RESET pullup voltage.  For example, if your /RESET pullup voltage is 5V and the MOSFET you choose has a threshold voltage of 1V, your microprocessor must provide a watchdog signal that is lower than 5V-1V=4V.  Also note that a FETs threshold voltage is the voltage where it starts to turn on.  You will need a higher gate voltage to turn the FET on hard enough to allow your uP watchdog signal to over ride the TPS3828 internal oscillator signal.

  • 0 in reply to Matthew Day
    Prodigy 30 points

    Michael: as drawn, the source goes to the watchdog device, and it's the drain that goes to the watchdog-kicker signal. So the watchdog-kicker signal voltage is irrelevant - it's the gate-source voltage that matters, and both of those are a function of the watchdog device.

    I did wonder if the source and drain were reversed on the drawing, and thought it through the other way - and it's still messy, for the reasons you give.

  • 0 in reply to Matthew Day
    Genius 5355 points

    Hi Matthew,

    What is the maximum pull down value allowed on the WDI pin (pin 4) to keep the watchdog enabled?

    Thanks.

  • 0 in reply to ikon
    TI__Guru 55940 points
    Hi Ikon,

    We recommend a 1k pulldown resistor. The voltage on WDI must be below 0.3V in order to be logic low. The current through this resistor can be up to 190uA. As a result, you will want to stay close to the 1k recommendation.

    Very Respectfully,
    Ryan