Sequencers

Forum Post: RE: UCD90160 sequence 18 voltage rails

Brad — Fri, 07 Jun 2013 13:40:00 GMT

No, the specification indicates that the UCD90160 is a 16-Rail Sequencer and Monitor.

Forum Post: UCD9081 I2C transition stretch issue

Max Han — Fri, 07 Jun 2013 06:27:00 GMT

UCD9081 I2C has a transition stretch issue in customer's projects.

if UCD9081 and other chips with SMBus function are connected to one I2C bus. During other chips with SMBus function thansfer data with master chip, if below conditions are all met, there will be a fault occured.

(1). stretch occurs when chips with SMBus transfer data with Master chip.

(2). stretch time is larger than 4ms.

(3). at the stretch ending time, the data on SDA line is just the same with UCD9081's address.

if all conditions above are met, UCD9081 will give a response because it faultly thinks this is an address. this response will make data transfering fail.

so how to prevent this falut response of UCD9081 occuring? could you give some suggestions?

UCD9081 is used in many this customer's projects, this issue result in many projects delay.

thank you!

Blog: Announcements

Heather Weir — Tue, 04 Jun 2013 20:49:00 GMT

Forum Post: UCD9090 GPI active low problem

Andrew Dyer — Mon, 03 Jun 2013 23:45:00 GMT

I am trying to set up a GPI on UCD9090 as active low. In off-line mode I can set this and 'write to hardware' with no problem. If I do the same thing on the real device connected with USB-I2C cable I get an error, the device resets and subsequent writes fail. After the error/reset the GUI reloads the settings from the hardware and I lose all the changes I've entered. To my mind there are 2 issues 1) why does the off-line and on-line modes behave differently? 2) is there some way to keep the GUI from losing changes when it reloads the settings after the error?

For the test below I changed GPIO1 from active high to active low and hit the .

1st message (copied to clipboard):

There was an error writing one or more parameters that are indirectly set by the Fusion Digital Power Designer:
GPI_CONFIG Write Inputs: Pin 4 GPIO1 ActiveLow Input,Pin 5 GPIO2 ActiveHigh Input,Pin 6 GPIO3 ActiveHigh Input,Pin 22 GPI1_PWM1 ActiveHigh Input,Pin 23 GPI2_PWM2 ActiveHigh Input,Pin 30 TMS_GPIO21 ActiveHigh Input,Pin 24 GPIO15 ActiveHigh Input,Pin 25 GPIO16 ActiveHigh Input [0x79858D454D6DA5AD4000000000]: NACK

2nd message (transcribed by me):

Fusion Digital Power Designer detected that the UCD9090 @ Adress 65d was reset. All device parameters will he refreshed when you clikc the OK button.

versions:
UCD 9090 ID string is UCD9090|2.3.5.0000|110701
USB adapter firmware 1.0.11
version 1.8.325 of the power designer software.

Forum Post: UCD90160 - 16 rails and ON / OFF sequencing of two groups

Adam Polus — Mon, 03 Jun 2013 22:22:00 GMT

I am at the detailed design stage of my project. I am using TI Fusion Digital Power Designer v1.8.325 in Offline mode (no board yet) to prove the schematic required logic can be implemented in the UCD90160.

I have got the complex project and I am strugeling with setup/configuration of the UCD90160.

Total of 16 monitored and sequenced rails.

Two rails shall be enabled in one after another sequence trigered on the Vin.

Other 14 railes are to be seqenced ON and OFF based on eather of two inputs.

I have got 1 rail which is to be part of the ON / OFF sequence, not monitored but PGOOD of this DC-DC conv to be sensed.

I have got 3 railes which are enabled but not monitored.

I have set all 14 to be sequenced ON/OFF railes as "control pin only".

Question1: Can sequencing be trigered by other input then PMB_CTRL or is it the only input which can trigger seqence ON and OFF.

Question2: I have managed to create required ON sequence (based only on PMB_CTRL) but I am unable to create reversed OFF sequence. This is becasue OFF sequencing isn't behaving as expeceted looking at the "timimg" graph (it is not behaving the same Sequence ON). Most but NOT ALL railes don't respond to seting its "sequence OFF dependency". Bug or is there some requirement that I have missed / haven't found???

Question 3: I expect that if all rails turn_off timing=5ms and Rail_1 is Sequence off dependency of Rail_2 and Rail_2 is Sequence off dependency of Rail_3 that on the PMB_CTRL going inactive in time=0ms then Rail_3 disabled @ t=5ms, Rail_2 disabled @ t=10ms and Rail_1 disabled @ t=15ms. Am I expecting correct?

Adam

Forum Post: RE: Does UCD9081 EVM GUI support Window7-64bit?

Daniel Katz — Fri, 31 May 2013 19:26:00 GMT

Hi Shannon,

The UCD9081 EVM GUI does support Windows 7 64-bit. It was updated in March. You can download it here.

Regards,

Dan

Forum Post: RE: UCD9090 - UCD90SEQ48EVM-560

Daniel Katz — Thu, 30 May 2013 23:20:00 GMT

I have not seen this type of issue before. It might be related more to some of your settings of Windows - resolution, text size, etc. What version of Windows 7 are you using? You could also try uninstalling and re-installing the software.

Forum Post: RE: Lm3881 Cadj mininum

LeonardEllis — Tue, 28 May 2013 20:44:00 GMT

Hi Alex,

Here's a rather detailed analysis on CadjMIN. Note that there is a large window on the time delay, that will have to be taken into consideration for the design - basically, based on simulations and adding margins, the CMIN is 200pF. Here are the details:

The clock period Tnom=Cadj *[(Vhth-Vlth)/ Itadj_src + (Vhth-Vlth)/Itadj_snk]

Slowest clock (min Itadj, max Vhth, min Vlth):

T=Cadj * [1.52*(Vhth-Vlth)/ (0.33 x Itadj_src) + 1.52*(Vhth-Vlth)/ (0.33 x Itadj_srk)] = 1.52/0.33 x Tnom = 4.5xTnom

Fastest clock (max Itadj, min Vhth, max Vlth):

T=Cadj * [0.42*(Vhth-Vlth)/ (1.67 x Itadj_src) + 0.42*(Vhth-Vlth)/ (1.67 x Itadj_srk)] = 0.42/1.67 x Tnom = 0.25xTnom

The above spread is independent of the value of Cadj. The same percentage error exists whether Cadj was 10nF or 200pF - just centered around a different Tnom. The LM3881 will eventually not match EC table if you take Cadj low enough due to the finite propagation delay of the comparator that sets the Cadj ramp peak-to-peak amplitude. As Tnom gets to be of the same order as the comparator prop delay, overshoot will occur on both the low and high peaks more and more. There appears to be no problem with the digital logic timing even going down to a Cadj of 1pF - so the comparator is the bottle neck.

In simulations it looks like this sets the min Tnom around 2.5us. Accounting for variations in the charging currents and layout parasitics this should be pushed out to Tnom>25us. That sets the minimum Cadj to 200pF. At that value the EC table values will still hold up; the designer will have to decide whether they can live with the 1/4 to 4x spread.

Forum Post: RE: UCD9090 program SVF file with JTAG

Daniel Katz — Thu, 23 May 2013 15:54:00 GMT

Does your tester have the PLD ISP Software option? The Agilent 3070 should be able to accept SVF files with this.

-Dan

Forum Post: RE: UCD90160 Firmware version verification

Daniel Katz — Tue, 21 May 2013 22:18:00 GMT

Hi Andre,

The device ID and firmware version are found at address 7F58 in the program flash and consist of up to 32 bytes of data bytes. When a part is connected to the computer, you can verify this in the Fusion GUI by going to "Tools" -> "Memory Peek/Poke/Dump" -> select "Memory Dump" -> type 7F58 into "Start Address" and type 32 into "# Bytes to Read." Select Read and it will read back the data bytes and the ASCII text equivalent.

Regards,

Dan

Wiki: Design Notes

Anonymous — Tue, 21 May 2013 16:08:00 GMT

Forum Post: UCC2946: Maximum watchdog period? Version with open drain or collector outputs?

Gilbert Pesant — Fri, 17 May 2013 21:02:00 GMT

Hello,

I am looking for a microprocessor supervisor circuit with watchdog, that can produce a 120s (nom) watchdog delay.

We also need industrial temperature range.

The UCC2946 is promising, but the spec doesn't show the max value (if any) for the watchdog timing capacitor (CRP).

Questions:

1) can a CRP = 4.7uF ceramic, X7R type capacitor be used, to produce a (near) 120sec nominal watchdog period?

2) is there a maximum value for CRP?

3) Do you have a version of this IC with open collector/drain outputs for RESET and WDO outputs?

4) Do you have other parts that can generate a 120s nom. watchdog delay (or close to that)?

Thank you!

Forum Post: BQ2954 power management IC

Ashik Das — Wed, 17 Apr 2013 02:10:00 GMT

Hello Sir/Madam,

I have question regarding your product BQ2954 power management IC. This following IC i am using for my University senior project to charge a 1-cell 3.7v Lithium-Ion battery. I used a circuit that is given on the data sheet (http://www.ti.com/lit/ds/symlink/bq2954.pdf). Also, i am using some of the replace parts according to it's similar specification. The replacement part i selected are:

FMMT3906 with 2n3906

FMMt304 with 2n3904

FMMT451 with TIP29

FMMT3904 with 2n3904

FZT789A with TIP32AG

I followed the exact circuit as shown in the data sheet (figure 3), however when i connect the rechargeable battery to out put battery terminal it shows the increase of current in power supply but at pin 2( CHG) there is no voltage and at pin3 BAT show low (0v). Also, the LED at pin 15 LED/CSEL show HIGH but at absence of battery it remain HIGH until i turn of the power supply. Please help me because i need to complete my senior project by MAY 7th.

Also,
1) We are connecting 1 cells in series, total battery pack voltage for the 1 cells is arnd 3.7V (arnd 3.3V per cell).

3) The reason we can't use a new IC as you suggested is because, this is our Final Year Project, and it ends this month by the end of may 7th. Thus we do not have enough time on our hand to implement a new circuit. So, since we have been researching and working on this bq2954 IC, we have almost got everything correct except this charging current. Thus,we hope to identify and rectify the problem with this IC itself, given the lack of time.

Some more info on our circuit when its charging the cells:
- Our bq2954 charger circuit is working on mode 3 (as set by the DSEL pin)
- When our battery is connected and the circuit is switched on the following is our LED statuses:
LED 1: ON

LED 2: OFF

CHG pin LED: OFF

BTST pin LED: ON
- And when our switched on but the battery is not connected, the following is our LED statuses:
LED 1: ON

LED 2: OFF

CHG pin LED: ON

BTST pin LED: ON
Thank you

Forum Post: UCD90120A watchdog input pulse width minimum time

Robert Rau1 — Tue, 16 Apr 2013 18:31:00 GMT

The data sheet references Twdi many times but the electrical specifications do not mention the minimum Twdi pulse width (low or high).

What is Twdi minimum low time?

What is Twdi minimum high time?

Forum Post: UCD9081 EVM not working / not detected

PS Narayanan — Thu, 11 Apr 2013 20:36:00 GMT

The UCD9081 EVM board is not detected by the PC I am using.

I downloaded the SW from the net, GUI version 3.0.0.15 from the web.

When I power up the board and it is attached to the PC, the SW is not able to

detect the UCD9081 (On the bottom right of the screen, I get a message that Windows

has installed the SW successfully).

I tried the ‘discover device’ option’ , the board still does not get detected.

I am using a Windows 7 PC.

Anybody have the same experience ? and found a solution?

Please let me know.

Thanks,

PS Narayanan

Forum Post: i bought a parts onreels,but der is no label marking,only i can see is d topmarking to56,for this topmarking what is d correct full part id?????

jovzz deelao — Tue, 02 Apr 2013 13:02:00 GMT

to56

Forum Post: UCD9090 Datasheet mistype?

Alexey Grehov — Thu, 21 Mar 2013 12:10:00 GMT

On page 26 of datasheet we have:

*****************
Power-Supply Enables
During reset, the GPIO pins are high-impedance except for FPWM/GPIO pins 17–24, which are driven low. External pulldown or pullup resistors can be tied to the enable pins to hold the power supplies off during reset. The UCD9090 can support a maximum of 12 enable pins.

NOTE
GPIO pins that have FPWM capability (pins 10-17) should only be used as power-supply enable signals if the signal is active high.

****************

Should it be pins 10-17 in both cases?

Forum Post: RE: Monitoring Voltages with Scaling Circuits

GaryS — Tue, 12 Mar 2013 21:18:00 GMT

Eric,

Would you have an answer to this post?

http://e2e.ti.com/support/power_management/digital_power/f/184/p/246891/870620.aspx#870620

Forum Post: Beagleboard I2C connection to UCD90xxx

Ted Lane — Wed, 06 Mar 2013 19:32:00 GMT

Has anyone used a TI Beagleboard or Beaglebone to control a UCD90xxx sequencer via I2C/smbus?

Ted

Forum Post: RE: UCD9081 doesn't drive outputs

Kirill Stepanov — Thu, 21 Feb 2013 08:38:00 GMT

Ok, I have another question: I try to read flash error log (starting from flash address 0x1000) and get array of 48 elements with value 0xff, while reading ERROR1-ERROR6 registers returns me values of 0.

Parameter IgnoreFlashErrorLog were set to values 0xFF (default), 0x01, 0x00 - no difference.

Is that situation normal?