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Q: TPS3809K33 power-up glitch by 11567
Im testing theTPS3809K33 as 2nd source to MAX809, and came across a power-up glitch. The glitch is short, but of significant magnitude, and likely occurs as a tracking of Vcc until the RESET becomes active (at 1.1V per the datasheet, plus small delay). It raises concern about causing possible latch-up in the ASIC that this SVS is reseting. Is this a known behavior or is this unexpected behavior? Would seem that a weak internal pull-down would be the best way to address this, but is there such a mechanism in the part? A: Re: TPS3809K33 power-up glitch by 10449
The TPS3809 internal circuitry can not actively control /RESET until the input voltage to the IC is >1.1V. This is normal behavior. Once the input voltage rises above 1.1V, the /RESET pin is actively pulled low and stays low until Vdd goes above the set threshold for the IC and stays there for the programmed delay time td. Only after these conditions are met will the /RESET pin go high and allow the processor to start. If the processor initially tries to start with Vdd<1.1V, it will immediately be pulled into the reset state as the input voltage starts to rise.
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