LM5069: Using DV/DT circuit results in circuit breaking WITHOUT current limit trip

Dan,

Assume Vscr = Vout above, correct?  You may be tripping CL, even though the scope shots indicate you are below the 24A lower trip point.  Is the Current measurement representative of I-in?  That is, make sure you capture the current that the Rsns sees, not Iout that will have the bulk caps in between the measurement and Rsns.  Capture the timer and get some higher resolution scope shots to help zero in.  I recommend you try:

1)  RC filter between Sense and Vin.  5 ohm, 1uF to start with but you can trial and error to help find cause with higher C (not meant as a production fix if too large value, just a problem identifier).

2) After above and as part of RC above, divide the signal down with 5 ohm Rsns to Sense and maybe 10 ohm across the cap (sense to Vin).  Make sure you don't put any resistor in the Vin line as the bias current for the device will flow through it and affect (reduce) the sensing signal.

3) Check layout of Vin and Sense routes.  Vin carries bias so if you have long thin etch, you will affect the current sense to the IC.  Make sure both are kelvin connected at the Rsns with Vin being a thick etch.  Sense doesn't have to be so thick as current on it is much lower.

4) Make sure Vin cap (C169) is right at the Rsns+ side.  This provides best filtering for the IC and input noise impace on current sense as it converts DM noise to CM and the IC rejects this very well.

5) Go to www.ti.com/hotswap and download the design calculator tool (excel).  Very useful.  With the FET you used, SOA is good.  But you have Plimit set too low at 108W.  It needs to be >150W.  Rpwr = 38k.  This isn't your issue at the moment but will come into play when you build quantity. 

6) Also not your immediate issue, but your design lacks a front end TVS and Output Schottky.  It will not survive Hot Shorts on the output without these.  Maybe not a requirement you have but if you do need to survive these, add these components and size as needed.  These are large devices.

Brian

Brian Daugherty said:

Dan,

Assume Vscr = Vout above, correct? >> CORRECT

You may be tripping CL, even though the scope shots indicate you are below the 24A lower trip point.  Is the Current measurement representative of I-in?  That is, make sure you capture the current that the Rsns sees, not Iout that will have the bulk caps in between the measurement and Rsns. 

I do not think that I am tripping the current limit. My current probe is on the input side of the breaker, so it definitely is capturing I-in, yes.

Having said that, I have to admit that it is strange that I do seem the Ctiming (C129) voltage start to ramp up toward the 4V threshold and perhaps reach it (this waveform is not included in
the current scopeshots). When I was testing a while ago and seeing these false trips, at the time I was monitoring Ctiming as well and do not recall seeing its voltage start to ramp. Since the
the current does not appear to be close to the limit, I am assuming that maybe the power limit is being reach as Vout drops. I did note however, that upon zooming into one of these waveforms
that Vout dropped BEFORE Vtiming started to ramp, maybe indicating that the power limit is being reached. But the question is why does Vgs start to drop?

Vin and Vout both vary up and down under normal motor load so the controller does have to control Vgate appropriately to maintain a Vgs of 12V. Can it do this even with a capacitor attached?
My thinking is C254 will follow Vgate when charging slightly but discharging Q37 will discharge C254 faster so it will not follow Vgate as readily.

As you said, I will have to capture better resolution scopeshots and send them. I will also increase Rpwr as you mentioned.

Capture the timer and get some higher resolution scope shots to help zero in.  I recommend you try:

1)  RC filter between Sense and Vin.  5 ohm, 1uF to start with but you can trial and error to help find cause with higher C (not meant as a production fix if too large value, just a problem 

2) After above and as part of RC above, divide the signal down with 5 ohm Rsns to Sense and maybe 10 ohm across the cap (sense to Vin).  Make sure you don't put any resistor in the Vin line as the bias current for the device will flow through it and affect (reduce) the sensing signal.

3) Check layout of Vin and Sense routes.  Vin carries bias so if you have long thin etch, you will affect the current sense to the IC.  Make sure both are kelvin connected at the Rsns with Vin being a thick etch.  Sense doesn't have to be so thick as current on it is much lower.

4) Make sure Vin cap (C169) is right at the Rsns+ side.  This provides best filtering for the IC and input noise impace on current sense as it converts DM noise to CM and the IC rejects this very well.

Current sense resistor and C169 and closely placed to the controller and Kelvin connections for sense resistor are good and short. I know from prior experience with this same layout
that the CL works pretty well both with an electronic load ramping a DC load and with a motor (inductive load). Without the DV/DT circuit, the breaker does NOT trip as easily as it seems
to be tripping with it present. In fact, all I did was remove the circuit and I am able to resolve the false trips.

5) Go to www.ti.com/hotswap and download the design calculator tool (excel).  Very useful.  With the FET you used, SOA is good.  But you have Plimit set too low at 108W.  It needs to be >150W.  Rpwr = 38k.  This isn't your issue at the moment but will come into play when you build quantity. 

I will try increasing the Rpwr value and see what happens.

6) Also not your immediate issue, but your design lacks a front end TVS and Output Schottky.  It will not survive Hot Shorts on the output without these.  Maybe not a requirement you have but if you do need to survive these, add these components and size as needed.  These are large devices.

Understood. I have TVS parts on the input (not shown here on this schematic). 

Brian

Brian,

After increasing the power limit to 400W, Rpwr (R109) = 100K, I captured the following scopeshots which are more zoomed in and display is set to continuous now instead of discrete as before.

In the first capture, CH1 = I-in (10mV / A, 10A / division), CH2 (purple) = Vgate-gnd, CH3 = Vsrc-gnd, CH4 = Vtiming. Note that Vtiming does not start to rise until Vsrc (Vout) has fallen significantly
from its nominal of 50V. Also, Vtiming never reaches its breaker threshold of 4V. Vdrain is not shown here but it is in the next capture.

In the second scopeshot, CH2 (purple) = Vdrain-gnd now. But the situation is similar with the drop voltage across the FET begin visible in 
the difference between CH2 and CH3 wavefroms.

Note that in neither of the scenarios does I-in even reach 20A or even close to the CL of 27.5A.

Hello Brian,

Do you any suggestions on how to resolve the issue. I have an idea for brute force method of fixing the problem. This is the
first attached schematic shown. Basically, I leave the dv/dt circuit but add in some method of switching the circuit in and out
based on the state of the breaker. It is shown here in the schematic as SPDT switch. A real implementation would involve some
optcoupler and transistors controlled by some comparator logic using the voltage state of the output and PG as inputs to control
what state the switch is thrown. Shown here:

MOTOR_POWER_CIRCUIT_BREAKER_Mod.PDF

My second idea is to change the position of the dv/dt capacitor to between the gate and drain. The slow turn on would be roughly the same. But operational fluctuations in Vsrc and Vdrain
would hopefully be more followed by Vgate while maintaining a Vgs of 12V.

The second schematic is shown here:

MOTOR_POWER_CIRCUIT_BREAKER_Cap.PDF

Can you let me know what you think?