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LM5060-Q1: Not able to drive the High side switch for 48V input with LM5060

Part Number: LM5060-Q1
Other Parts Discussed in Thread: LM5060, LM5069, TIDA-01168,

Hi ,

We have used LM5060 for 48V side bus as a output protection device.Its an Automotive application. We are using two MOSFETs (IPB180N10S402ATMA1 )are connected in series .

We are not able to drive these MOSFETs ,We have forced deactivation for UVLO and OVP.  I have attached the waveforms also , Please help us to resolve these issues. I have also attached schematic 

  • Hi Raghavendra,

    Welcome to E2E! Can you reupload the waveforms and schematic drawings?

    I suggest taking a look at our Design Calculator for the LM5060. The calculator will help determine if the schematics/MOSFETs are ok or not. The calculator will also explain why UVLO are OVP deactivated.  After the calculator is filled out, we will be able to assist you further with the additional information. 

    Some of the data you will need for the calculator includes total Cout (all downstream capacitance including LC filters in DC_DC converters), load parameters, thermal environment (max ambient and theta pcb to ambient), and full VIN range. 

    For help on filling out the calculator tool, we have video tutorials. The videos explain how to enter the correct values cell by cell. The videos are located here

    Let me know if you have any questions,

    Arthur Huang

  •  Hi Arthur,

    Thanks for your reply, we have used Design calculator for LM5060 ,  We did below changes in the schematic (attached below )

    Ctimer = 3  363nF (220nF|| 100nF|| 33nF )

    R181=  2K ( Gate series resistor )

    removed C145 ,C24  (connected between OUT pin PGND )

    It worked for some time and we tried testing it with capacitors between OUT and PGND , after that it stopped working.

    We are using IPB180N10S402ATMA1  MOSFET with 200nC Qg and 2.5mohms

    Sometimes we see voltage on nPGD is more than 0.4V , does it mean is it due to VDS fault delay ?

    Also in TIDA-001168 schematic,  47nF is being used  for Ctimer , for 48V side protection ,please suggest

    can we force deactivation of UVLO and OVP  and test or it is mandatory  to have.

    Regards,

    Raghavendra

  • Hi Raghavendra, 

    I took a look a the provided schematic, and it seems that your UVLO and OVLO thresholds are set incorrectly for 48V operation. The OVP is currently set at around 25V while your UVLO is around 7.22V, which is low for a 48V application. This can cause an inrush event as the FET voltage rises from 7.22V to 48V and DV/DT changes. 

    I would recommend testing the current setup at 20V and seeing if it works with the current UVLO and OVLO. If it works correctly, then we know that the circuit is set up properly. After that, calculate different UVLO and OVLO resistor values and make sure they work with the input voltage range. 

    Let me know if you have any questions,

    Arthur

  • Hi Arthur,

    We tried with 12V, we also forced UVLO to high and OVP to low (disabled UVLO and OVP ). It dint work.
    MOSFET enhances up to 2V sometimes but not fully .Ctimer values are changed as per the recomendations from the datasheet (47nf--68nF ). Just to test we have also tried with MOSFETs with low Vgs(th), it didnt help.
    what could be the other reasons ?

    Thanks and Regards,
    Raghavendra
  • Hi Arthur,

    Is any updates available for the above query.

    Regards,
    Raghavendra
  • Hi Raghavendra, 

    Apologies on the delay. So the device does not work at 12V even with UVLO and OVP disabled?

    If the MOSFET is not fully turning on, it might be an issue with the gate enhancement. What type of load are you driving downstream, and what is your output capacitance? I put your information into the calculator myself and everything seemed to be nominal, so you are within SOA and normal operating conditions. 

    Can we get some oscilloscope shots, similar to the ones found on page 25 of the datasheet? This will give us a better indication on why the FET isn't turning on.

    Thanks,

    Arthur

  • Hi Arthur,

    Thanks for your reply, our 48V Circuit breaker is working now , We followed LM5060 calculator , Changed Ctimer =100nF, Cgate=4.7nF , added 10uF to the output . Thanks for your support .

    Thanks and Regards,
    Raghavendra
  • Hi Arthur,

    With respect to TIDA-0068 document, can isolation of 500VDC be achived between 12V and 48V galvanic groups or galvanic isolation is necessary. We are designing a solar converter module for Automotive application , it should comply with LV148 . Please suggest.

    Thanks and Regards,
    Raghavendra
  • Hi Arthur ,


    48V /12V circuit break works fines when no load is connected but it turns off the Gate when load is connected (4.8 ohms ) . We are having 14K ohms for Rs (current limiting resistor ) . Please suggest.


    Thanks and Regards,
    Raghavendra
  • Hi Raghavendra,

    Can you tell me which TI Design you are referring to? I am not familiar with the one you mentioned, but I could look into it.

    Thanks,
    Arthur
  • Hi Arthur,
    I am reading to TIDA-0068 document, please sucan visitation of 500vdc be achieved between 12v and 48v Galvani group S
    Also LM5069 device not driving the gates when we have connected loads across 12v and 48v net , please suggest.

    Thanks and regards,
    Raghavendra
  • Hi Arthur,

    I am referring to TIDA-0068 from TI , does this design comply with LV148 standard i.e. is isolation between 12V and 48V groups is 500VDC (leakage current <1uA ) . Please suggest.

    Also the LM5060 is working when no load is connected across the OUT pin , and the gate is not deiven when the OUT is connected with a load of 500mA . Please suggest we are struck due to this .

    Thanks and Regards,
    Raghavendra
  • Hi Arthur ,

    A small typo error , please correct TIDA-0068 as TIDA-01168

    Regards,
    Raghavendra
  • Hi Raghavendra, 

    I would recommend starting another E2E thread for the TIDA question, I am not familiar with the TI Design. 

    Regarding the LM5060-Q1, you changed the OVP and UVLO thresholds correct? If so, then I think the issue might be with your timer capacitance. Can you attach waveforms of the device turning on/off and attach a scope to the Timer pin? My guess is that the device is latching off whenever the FET is enabled, but I need some waveforms to check. Also include input current, and input/output voltage on the waveforms.

    Thanks,

    Arthur

  • Hi Arthur,

    Regret for the delay, i am referring to TIDA-0068 . Please provide more information on how to achieve galvanic isolation between 12V and 48V groups.

    Thanks and Regards,
    Raghavendra
  • Hi Raghavendra, 

    Unfortunately, this is not the correct forum post for this question. I am unfamiliar with TIDA-0068 and won't be able to assist you, you will need to start another forum post on E2E for someone to help you with galvanic isolation. 

    Please let me know if you have any more questions specifically regarding the LM5060-Q1. 

    Thanks,

    Arthur