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LM5069: Failure output in case of startup

Hirotaka Matsumoto
Guru 27525 points
Part Number: LM5069
Other Parts Discussed in Thread: CSD19502Q5B

Hi all

Would you mind if we ask LM5069?
Please refer to the attachment file.

20180123_LM5069.pdf

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Expert 5940 points

    LM5069_Design_Calculator_REV_B per sch inputs needs work.xlsxHirotaka,

    The design needs a lot of work.  1st FET selection:  This Infineon FET is a poor choice for hotswap.  It has extremly bad SOA, not suitable and may be too high Rdson depending on your operation current.  Look at the CSD19502Q5B as a start.  You may need even a stronger SOA than that.  You need a much higher value dv-dt cap vs the 330pF.   Timer is too short with 100pF.  Go to www.ti.com/hotswap and download the design tools needed. There are excellent app notes and tutorial video on using the tools.  I attached a 1st cut tool per the schematic.  This should get you a start.  Note the red items in the spreadsheet need to be corrected.   You need to know the entire Cout downstream, not just what is on the schematic page sent, along with all of the system requirements.

    Brian

  • 0 in reply to Brian Daugherty
    Guru 27525 points

    Brian san

    Thank you so much for your reply!
    We got that customer's FET is not suitable, so we encourage the customer to change FET.

    And then, we would like to confirm as follows;
    ・You need a much higher value dv-dt cap vs the 330pF.
    ・Timer is too short with 100pF.
    By increasing Ctimer, it expands the minimum fault time (tflt).
    There is the description on the datasheet  "the minimum fault time (tflt) to be greater than the start time (tstart) by adding an additional margin of 50% of the fault time."
    Does it mean  tflt+margin > tstart?

    And then, about dv-dt cap vs the 330pF, does it require to slow the rising time?

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Brian Daugherty
    Guru 27525 points

    Brian san

    And then, our customer changed Ctimer, after that they could solve the problem.
    Thank you for your advice.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Expert 5940 points
    Hirotaka,

    Take care of anything in the spreadsheet that doesn't look good, including the dv_dt cap. If you have large Cout, you will power up into Pwr Limit and activate the timer. You may exceed the FET rating or a timing issue. dv_dt slows rise time so Plim isn't active and no timer active. Note your Plim was set a little low also so you need to increase it a little.

    Brian