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Part Number: TMS320C6678
I modified the PCIe example project to set it up in PHY loopback mode. I followed the steps listed in the user manual and it looks like everything is working but I'm seeing some strange behavior.
After I send the data from RC, I query the fatal, non-fatal, correctable, unsupported request error bits in the DEV_STAT_CTRL register. The unsupported request error bit is always coming back as a 1, along with the non-fatal error bit. But, the destination buffer matches the source buffer and I see "Root complex received data" message in the console.
Any thoughts on why those bits are being set to 1 and yet the loop back mode succeeds?
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In reply to Cvetolin Shulev-XID:
In reply to lding:
You are right, I modified the existing project to support PHY loopback mode.
I noticed that those error bits are being set even before the data is being sent. The LTSM value is 11 as expected and I see "Link is up" message on the console.
I made PCIE_OB_LO_ADDR_RC and PCIE_IB_LO_ADDR_RC the same to get this to work. The data I send is correctly echoed back into the appropriate buffer, but I don't know why those error bits are being set.
In reply to VineyK:
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