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Part Number: TMS320DM6467
We use the TMS320DM6467ZUTA for H.264 video decoder,the video data is put out by VPIF interface,We use an external clk input to VPIF's VP_CLKIN0 pin from a FPGA' s PIn in the board,the output video data is put on the negative edge of the VP_CLKOUT2 pin, The FPGA receive the output video data on the resedge of the VP_CLKOUT2 in the image proceesor board. for some design constraint,We must use the FPGA's inner clk with a fixed phase from the VP_CLKIN0 to recevice the output video data for another pass ,We want to know the delay phase bettween VPIF's VP_CLKIN0 and VP_CLKOUT2 in the TMS320DM6467ZUTA ,please sure the delay phase from the input and output pin,because We can't find the data from the device datasheet. and We wonder if it's a fixed delays phase in your device?
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In reply to Pavel Botev:
We don’t think
Th VPIF_clkout2 is controlled by SW,because from the data sheet of dm6467 and the VPIF userguide,it’s just a MUX selector and the video data put on the either edge of the clockout controlled by SW. We think it’s a fixed phase delay when the SW set the edge of the clock
In reply to user1063570:
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