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TMS320C6678: VCNTL[3:0] VID Interface timing

Part Number: TMS320C6678

From SPRS691E Figure 7-5 SmartReflex 4-Pin VID Interface Timing - it's not clear when VCNTL 6-bit sequence starts (when VCNTL3 goes low), especially because on ref. designs these open drain pins are connected to pull-ups to VCCIO_18 that can be provided with delay relative to CVDD.

1. Is it started only after VCCIO_18 is applied and VCNTL3 goes high (in other words it waits for pull-ups)?

2. If yes - how long delay between CVDD and VDDIO_18 is allowed (how long CVDD can be kept at 1.1V default start-up voltage)?

3. if not - who initiates 6-bit transfer / VCNTL3 falling edge (for example to LM10011 )? Is VCCIO must be supplied before CVDD because of pull-ups?

  • The team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • In reply to Cvetolin Shulev-XID:

    Edward,

    1. Is it started only after VCCIO_18 is applied and VCNTL3 goes high (in other words it waits for pull-ups)?

    Please make sure to follow the power, clock and reset sequencing defined in the Data Manual.  All supplies must be valid in the proper order before PORz and RESETFULLz are taken high.  The VCNTL pins will then signal the VID value some time later.  Therefore, the pull-ups are active long before the VCNTL pins begin their sequence.

    2. If yes - how long delay between CVDD and VDDIO_18 is allowed (how long CVDD can be kept at 1.1V default start-up voltage)?

    Please see required power sequence.

    3. if not - who initiates 6-bit transfer / VCNTL3 falling edge (for example to LM10011 )? Is VCCIO must be supplied before CVDD because of pull-ups?

    See above.

    Tom

     

     

  • In reply to Tom Johnson 16214:

    Tom

    I understand power, clock and reset sequencing defined in the Data Manual very good. 

    Please clarify "The VCNTL pins will then signal the VID value some time later" - later from when? Are VCNTL pins activated only after PORz and RESETFULLz are taken high?

    Please confirm that, because I can't found that VCNTL are related to PORz and RESETFULLz in the Data Manual, according to Figure 7-5 (page128) it starts after CVDD is applied - please point me if you can, thank you. I want to be sure that VID value will be latched correct.

  • In reply to Edward L.:

    Edward,

    Yes, the VCNTL pins are undefined while the device is held in PORz or RESETFULLz reset.  The signaling on these pins will happen after all supplies valid and after device resets are released.  Some designs have needed to add logic between the VCNTL outputs and the power supply to prevent glitches generated during the power up sequence latching an erroneous VID value.

    Figure 7-5 simply shows that CVDD had to reach its final value some time previously.  The CVDD timing in this figure is about the adjustment of CVDD to the SRV level after the VID value is provided on the VCNTL pins.

    Tom

     

  • In reply to Tom Johnson 16214:

    Thank you for clarification.
    Just to understand it finally - this means that it is OK to keep CVDD at maximum voltage for some time until device will be unreseted?
    I need to understand this because we implement a complex system with tree TMS320C6678 using separate CVDD (due to SmartReflex) but common DVDD18, thus DVDD18 and resets will be delayed until all DSPs CVDD are OK, and I worry about keeping CVDD at max value 1.1V instead required by VID.
  • In reply to Edward L.:

    Edward,

    The plan is reasonable as long as the delay is not too long.  Please see the note above Figure 7-3:

    Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
    in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level
    within 20ms.

    Tom

     

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