This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: 66AK2G12
Hi K2G team,
My customer is nearing production with their K2G project, and they have an urgent board bring up issue:
"I just received my new board. This board is based on the design of K2G ICE board which has single DDR3L chip. My last board is based on K2G EVM it doesn’t have this issue.
After boot up the board and connected to DSP core(C66x) through JTAG. The reading of BOOTCFG_DEVSTAT Register is 0x005EFEBB which is not the desired values.
The bit of NODDR is 1. This disables EMIF and cannot access DDR3L.
The 4-bit LSB of BOOTMODE should be zeros. We have pulldown resistors, 4.7Kohms for those four pins. They should be 0000b(SLEEP mode for using JTAG) but it shows 1101b.
The LENDIAN is 0. The device endian mode is Big endian instead of desired little endian.
I am going to check PORn and bootmode pins during power up sequence, but can you help point me in the right direction to troubleshoot the undesired value of BOOTCFG_DEVSTAT .
Q1: The bit of NODDR is READ only according to K2G TRM. The pin of NODDR is unconnected in our hardware. Is there any way I can change it to 0?
18.104.22.168 BOOTCFG_DEVSTAT Register (Offset = 20h) [reset = 1h]
BOOTCFG_DEVSTAT is shown in Figure 5-8 and described in Table 5-33.
Indicates device bootstrap selection upon a power-on reset by PORn or RESETFULLn. The default value
of this register is determined by the bootstrap pins. Once set, these bits remain set until a power-on reset.
Q2: Which pin is the LENDIAN bootmode pin? I cannot find it in TRM.
22.214.171.124 BOOTCFG_SYSENDSTAT Register (Offset = 710h) [reset = 0h]
BOOTCFG_SYSENDSTAT is shown in Figure 5-95 and described in Table 5-294.
This register provides a way for reading the system endianness in an endian-neutral way from A15 core.
This register captures the LENDIAN bootmode pin. The value is latched on the rising edge of PORn or
more information here. See below for waveforms of their startup sequence.
The Ch2(blue color) is 3.3V for K2G’s DVDD33.
The Ch3(pink color) is 1.8V for K2G’s DVDD18, PLLs.
The Ch1(yellow color) is PORn signal. This is from PMIC TI’s TPS65400 PGOOD pin. It aligned with K2G’s CVDD (not shown on attached picture)
The Ch4(green color) is the BOOTMODE03 which is low on the rising edge of PORn. Actually, it’s low all the time as you can see in the picture. But the BOOTMODE03 in BOOTCFG_DEVSTAT register is HIGH. I just use one of BOOTMODE pins to be an example to show you why the BOOTCFG_DEVSTAT is not what I see on the waveforms of the BOOTMODE signals.
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Brian Antheunisse:
You mentioned that this design was based on the K2G ICE but that you are using the PMIC. Can you provide some additional detail on the design? In you statement above you said the PORn is aligned with the CVDD. What is the delay between CVDD and PORn? How are you clocking the part? When is the clock present?
If you need more help, please reply back. If your question is answered, please click Verify Answer
In reply to Bill Taboada:
Q1: My customer has modified their schematic a little to add a delay on the PORn signal. Can you let us know if this method will be sufficient?
Q2: During the measurement of power up sequence I noticed the amplitude of SYSOSC_IN is kind of small as you can see in the below picture.The Ch1(yellow color) is K2G’s SYSOSC_OUT. It swings between 0 to 1.8V. But Ch3(pink color), K2G’s SYSOSC_IN, only swings 0.45V to 1.3V.
Based on the datasheet, the VIL=0.35*1.8V=0.63V; VIH=0.35*1.8V=1.17V. we only have less than 0.2V margin for both VIL and VIH. Is there any concern about it? Do we need to improve it? If so, how? Could this be a load capacitance issue? The crystal we use has CL=12pF. The Cf1 and Cf2 (refer to datasheet Table 5.3) on our design is 22pF. If use Figure 5-16. Load capacitance equation in the data sheet. The Cf1 and Cf2 should be 24pF.
I also notice the old K2G datasheet for crystal shunt capacitance is TBD but the specification in new datasheet is max. 4pF. The crystal we use is ABM8AIG-25.000MHZ-12-2Z-T3. It was chose before the spec was available. Its shunt capacitance is max. 7pF. What would happen if shunt capacitance is out of spec?
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.